Path Specific Register Design to Reduce Standby Power Consumption

Emre Salman,Qi Qi

doi:10.3390/jlpea1010131

Abstract

A methodology is proposed to design low leakage registers by considering the type of timing path, i.e., short or long, and type of register, i.e., launching or capturing. Three different dual threshold voltage registers are developed where each register trades, depending upon the timing path, a different timing constraint for reducing the leakage current. For example, the first proposed register is used as a launching register in a noncritical path, trading clock-to-Q delay for leakage current. Other timing constraints such as setup and hold times are maintained the same not to introduce any timing violations. Alternatively, the second and third registers, trade, respectively, setup time and hold time for leakage current while maintaining clock-to-Q delay constant. The effect of the proposed methodology on leakage current is investigated for four technology nodes. The overall reduction in the leakage current of a register can exceed 90% while maintaining the clock frequency and other design parameters such as area and dynamic power the same. Three ISCAS 89 benchmark circuits are utilized to evaluate the methodology, demonstrating, on average, 23% reduction in the overall leakage current.

Highlights

Power dissipation is a primary limitation to further expand the capabilities of modern CMOS integrated circuits
Only the dynamic power is affected by the clock frequency whereas the overall static power continues to increase due to higher leakage current
The overall reduction in leakage current is compared for each case in four different technologies

Summary

Introduction

Power dissipation is a primary limitation to further expand the capabilities of modern CMOS integrated circuits. Miniaturization of the physical dimensions and advanced manufacturing technologies such as 3-D integration [1] and system-in-package [2] have tremendously increased the integration capability where power consumption has become the primary design barrier. Power supply voltage has been reduced to satisfy reliability constraints. Decreasing the power supply voltage requires the threshold voltage to be reduced to maintain high drive current capability. The reduction of the threshold voltage, exponentially increases the subthreshold leakage current [5]. A reduction in the gate oxide thickness exponentially increases the mechanical tunneling of the carriers through the oxide, producing significant gate leakage current [6].

Methods

Results

Discussion

Conclusion