Comprehensive Design and Timing Analysis for High speed Master Slave D Flip-Flops using 18 nm FinFET Technology

Abstract

Ensuring correct functionality is the basic objective of any digital design and this can be done only if the circuit obeys all the timing constraints. Static Timing Analysis is the procedure performed to calculate the setup and hold time of any digital circuit and to check for any setup and hold time violations. This paper presents the methodology to perform setup and hold time analysis for different designs of Master Slave D Flip-Flop using 18 nm FinFET technology. FinFET technology was chosen since it is the prevalent technology in the industry. Implementation of D Flip-Flop design, suitable test circuit and timing analysis is performed on the Cadence virtuoso analog design environment tool. Using appropriate excitations, parametric analysis is carried out to obtain the setup and hold time values for various designs of D Flip-Flop including the proposed design. From the results, it was observed that the setup time and hold time varied with different clock edge rates. For the edge rates of 0.01, 0.05, and 0.1 ns, it was observed that the proposed design gave setup times of 54.9, 61.2, and 69.8 ps and hold times of −30.7, −43.6 and, −48.8 ps, respectively. On comparing all the results, it was observed that the GDI MUX and pass transistor-based designs gave a good trade-off between transistor count, setup time and hold time. For the proposed design, although the setup times were slightly on the higher side, the hold time values were more negative which is always preferred.