Clock skew optimization for maximizing time margin by utilizing flexible flip-flop timing

Abstract

Clock skew scheduling is one of the essential steps to be carefully performed during the design process. Two commonly used strategies for solving the task are the scheduling of clock arrival times under bounded clock skew constraint and the scheduling of clock arrival times under hold and setup time constraints. This work belongs to the useful clock skew scheduling. In comparison with the prior works in which the inter-dependent relation between the setup and hold times of flip-flops have never been exploited, this work addresses the clock skew optimization problem integrated with the consideration of the interdependent relation between the setup and hold times, and clock-to-Q delay of flip-flops, so that the time margin is more accurately and reliably set aside over that of the previous methods, which have never taken the integrated problem into account. Precisely, based on an accurate flexible model of setup time, hold time, and clock-to-Q delay, we propose a stepwise clock skew scheduling algorithm in which at each iteration, the worst slack of setup and hold times is systematically and incrementally relaxed to maximally extend the time margin. The effectiveness of the proposed method is shown through experiments with benchmark circuits, demonstrating that our method relaxes the worst slack of circuits, so that the clock period (T clk ) is shortened by 4.2% on average, namely the clock speed is improved from 369MHz∼2.23GHz to 385MHz∼2.33GHz with no time violation. In addition, it reduces the total numbers of setup and hold time violations by 27.7%, 9.5%, and 6.7% when the clock periods are set to 95%, 90%, and 85% of the value of T clk , respectively.