Gate Length Devices Research Articles

Microwave noise performance of AlGaN/GaN HEMTs

The authors have characterised the microwave noise performance of AlGaN/GaN HEMTs epitaxially grown on insulating SiC substrates. The minimum noise figure for 0.25 /spl mu/m gate-length devices was measured to be 0.77 dB at 5 GHz and 1.06 dB at 10 GHz. The measured minimum noise figures are comparable to those exhibited by GaAs-based FETs, which demonstrates the viability of AlGaN/GaN HEMTs for low-noise applications.

Highly suppressed short-channel effects in ultrathin SOI n-MOSFETs

We have investigated short-channel effects of ultrathin (4-18-nm thick) silicon-on-insulator (SOI) n-channel MOSFET's in the 40-135 nm gate length regime. It is experimentally and systematically found that the threshold voltage (V/sub th/) roll-off and subthreshold slope (S-slope) are highly suppressed as the channel SOI thickness is reduced. The experimental 40-nm gate length, 4-nm thick ultrathin SOI n-MOSFET shows the S-slope of only 75 mV and the /spl Delta/V/sub th/ of only 0.07 V as compared to the value in the case of the long gate-length (135 nm) device. Based on these experimental results, the remarkable advantage of an ultrathin SOI channel in suppressing the short-channel effects is confirmed for future MOS devices.

High-performance double delta-doped sheets Ga0.51In0.49P/In0.15Ga0.85As/ Ga0.51In0.49P pseudomorphic heterostructure transistors

Novel double delta-doped sheet (D3S) Ga0.51In0.49P/In0.15Ga0.85As/Ga0.51In0.49P pseudomorphic high-electron-mobility transistors (PHEMTs) have been fabricated successfully and studied. A wide-gap Ga0.51In0.49P Schottky layer and a D3S structure are used to improve device performance. Furthermore, an airbridge-gate structure is employed to achieve good dc and RF performances. For a 1 µm gate length device, a high gate-to-drain breakdown voltage over 35 V, an available output current density up to 615 mA mm-1, a maximum transconductance of 110 mS mm-1 and a high dc gain ratio of 487 are obtained. On the other hand, the maximum values of unity current gain cut-off frequency fT and maximum oscillation frequency fmax are 19.5 and 40.5 GHz, respectively. The output power of 15.6 dB m (363 mW mm-1), power gain of 5.6 dB, power added efficiency (PAE) of 37% and drain efficiency (DE) of 51% are obtained at an input power of 10 dB m and the measured frequency of 2.4 GHz.

A practical device scheme for designing the dopant profile of source/drain extension region in sub-quarter-micron p-MOSFET's

A practical device scheme for designing sub-0.25 μm p-MOSFET's has been examined with respect to the dopant profile of source/drain (S/D) extension. Though shallow junction was reported to be helpless to reduce short channel effect for devices with the same effective gate length ( L eff), shallow-junction techniques are critically important to the practical device/process design for controlling the overlap of S/D extension with the gate. Adjusting the lateral dopant diffusion of S/D extension by other processes except shallow junction techniques may degrade the process control and the resultant performance for devices of the target gate length. In terms of a practical IC technology for sub-0.25 μm p-MOSFET's, an L eff value properly smaller than the target gate length should be employed to well control the short channel effect and achieve the driving capability as large as possible. Hence, a scheme that properly adjusts the doping concentration for p-S/D extension formed by a given shallow-junction technique is significantly practical for designing the sub-0.25 μm p-MOSFET's with trade-off between driving capability and short channel effect.

Enhanced Two-Dimensional Electron Gas Confinement Effect on Transport Properties in AlGaN/InGaN/AlGaN Double-Heterostructures

A striking effect of polarization-induced electron confinement on transport properties has been observed in nitride double-heterostructures. The two-dimensional electron gas mobility has shown to be drastically enhanced in the AlGaN/GaN/AlGaN double-heterostructure, compared with that in the conventional AlGaN/GaN single-heterostructure. The observed mobility enhancement results from the strong polarization-induced electron confinement in the double-heterostructure. Device operation of an AlGaN/GaN/AlGaN double-heterostructure field effect transistor has been demonstrated: a maximum transconductance of 180 mS/mm has been obtained for a 0.4 μm gate length device. In the AlGaN/InGaN/AlGaN double-heterostructure, the increased capacity for the two-dimensional electron gas has been observed in addition to the enhanced electron mobility. The AlGaN/(In)GaN/AlGaN double-heterostructures are promising for field effect transistor applications because of their superior electron transport properties.

Metamorphic InAlAs/InGaAs enhancement mode HEMTs on GaAs substrates

In/sub 0.5/Al/sub 0.5/As/In/sub 0.5/Ga/sub 0.5/As HEMTs have been grown metamorphically on GaAs substrates oriented 6/spl deg/ off [100] toward [111]A using a graded InAlAs buffer. The devices are enhancement mode and show good dc and RF performance. The 0.6-/spl mu/m gate length devices have saturation currents of 262 mA/mm at a gate bias of 0.7 V and a peak transconductance of 647 mS/mm. The 0.6 /spl mu/m/spl times/3 mm devices tested on-wafer have output powers up to 30 mW/mm and 46% power-added-efficiency (PAE) at 1 V drain bias and 850 MHz. When biased and matched for best efficiency performance, this same device has up to 68% PAE at V/sub d/=1 V.

P-Type SiGe transistors with low gate leakage using SiN gate dielectric

Using high-quality jet-vapor-deposited (JVD) SiN as gate dielectric, p-type SiGe transistors are fabricated on SiGe heterostructures grown by ultra-high-vacuum chemical vapor deposition (UHVCVD). For an 0.25-μm gate-length device, the gate leakage current is as small as 2.4 nA/mm at V/sub ds/=-1.0 V and V/sub gn/=0.4 V. A maximum extrinsic transconductance of 167 mS/mm is measured. A unity current gain cutoff frequency of 27 GHz and a maximum oscillation frequency of 35 GHz are obtained.

Demonstration of submicron depletion-mode GaAs MOSFETs with negligible drain current drift and hysteresis

We successfully fabricated submicron depletion-mode GaAs MOSFETs with negligible hysteresis and drift in drain current using Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> (Gd <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) as the gate oxide. The 0.8-μm gate-length device shows a maximum drain current density of 450 mA/mm and a peak extrinsic transconductance of 130 mS/mm. A short-circuit current gain cutoff frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of 17 GHz and a maximum oscillation frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ) of 60 GHz were obtained from the 0.8 μm×60 μm device. The absence of drain current drift and hysteresis along with excellent characteristics in the submicron devices is a significant advance toward the manufacture of commercially useful GaAs MOSFETs.

SiGe virtual substrate N-channel heterojunction MOSFETs

Heterojunction MOSFETs (HMOSFETs), grown on a virtual substrate of SiGe and having a strained silicon channel, have been fabricated. A conventional silicon MOS process was used, including dry thermal oxidation and high temperature source-drain annealing. Good transistor I-V characteristics were obtained for devices having drawn gate lengths between 150 nm and 10 µm and an extrinsic transconductance of 220 mS mm-1 is reported for the 150 nm gate length device. Technology computer aided design (TCAD) is used to determine that the bulk low field mobility of the strained silicon which forms the channel is 1500 cm2 V-1 s-1, while the source-drain series resistance is 1.5 mm. Good agreement between simulated and experimental I-V data is obtained.

Growth of high performance InGaAs/InP doped channel heterojunction field effect transistor with a strained GaInP Schottky barrier enhancement layer by gas source molecular beam epitaxy

In this article, we present a systematic investigation of the Schottky characteristics of metal/Ga0.2In0.8P/InP. It is found that barrier heights of 0.6–0.7 eV are achieved for Schottky junctions formed on Ga0.2In0.8P/InP. Fermi level pinning occurs at the surface of the wet-etched Ga0.2In0.8P prior to metallization. No degradation in the Schottky characteristics is observed at temperatures as high as 250 °C. InGaAs/InP doped channel heterojunction field-effect transistors (HFETs) with a Ga0.2In0.8P Schottky barrier enhancement layer (SBEL) were grown and fabricated. The 0.25 μm gate-length devices show excellent dc and rf performance, with an ft of 117 GHz and an fmax of 168 GHz. These results suggest that GaInP is a promising material as a gate SBEL for InP based HFET applications.

Metamorphic In/sub 0.4/Al/sub 0.6/As/In/sub 0.4/Ga/sub 0.6/As HEMTs on GaAs substrate

New In/sub 0.4/Al/sub 0.6/As/In/sub 0.4/Ga/sub 0.6/As metamorphic (MM) high electron mobility transistors (HEMTs) have been successfully fabricated on GaAs substrate with T-shaped gate lengths varying from 0.1 to 0.25 μm. The Schottky characteristics are a forward turn-on voltage of 0.7 V and a gate breakdown voltage of -10.5 V. These new MM-HEMTs exhibit typical drain currents of 600 mA/mm and extrinsic transconductance superior to 720 mS/mm. An extrinsic current cutoff frequency f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> of 195 GHz is achieved with the 0.1-μm gate length device. These results are the first reported for In/sub 0.4/Al/sub 0.6/As/In/sub 0.4/Ga/sub 0.6/As MM-HEMTs on GaAs substrate.

Design Aspects of a Submicrometer Gate Length High Electron Mobility Transistor

An optimized model based on the solution of two-dimensional Poissons equation with improved performance for design aspect of a submicron gate length device is proposed. It analyses the dependence of threshold voltage on the process parameters and gives an idea about the choice of the doping concentration and AIGaAs layer thickness to obtain a minimum threshold voltage variation. The model discusses the different short channel parameters with their effect on the subthreshold current. When calculated results from the present model are compared with available experimental aata, a close agreement between the two is observed, thereby, confirming the validity of the model.

Diamond junction FETs based on δ-doped channels

Abstract Diamond junction field effect transistors (FETs) utilizing δ-boron-doped diamond films were fabricated and analyzed. In order to allow full charge modulation by the gate, the total channel sheet charge must not exceed the order of 1013 cm−2. However, boron doping shows full activation only for concentrations above ca 1020 cm−3 [1] . This yields a thickness for a fully activated channel in the range of ca 1 nm. To approach such narrow doping spikes any parasitic boron doping tails need to be eliminated. One possible way of achieving this is to compensate boron doping with nitrogen doping, an extremely deep donor. This results in the formation of a pn-junction, where the nitrogen doped part is not activated at room temperature and which therefore represents a semi-insulating (lossy) dielectric at low temperature and high frequency. At elevated temperature and low frequency the nitrogen doped layer becomes conducting acting as a series resistor to the interfacial pn-junction. Using this concept of a lossy dielectric pn-junction in the δ-doped channel FET, two gate diode configurations were investigated. In the first the nitrogen doped (Ib) synthetic diamond substrate served as a large area back gate, while in the second the nitrogen doped gate layer was grown on top of the δ-channel. The devices show high drain currents of up to 100 mA mm−1 and full channel modulation even at moderate operation temperatures of 200–250 °C. By extrapolation a current density of 1 A mm−1 is expected for a 0.25 μm gate length device.

Novel integrated photodetector on Si LSI circuits. Optically controlled MOSFET

We have demonstrated a novel integrated photo-detector on Si large-scale integration circuits. This device integrated the light absorption region on the gate of metal-oxide-semiconductor field-effect transistor (MOSFET), and the long wavelength light controls the current of MOSFET. The GaInAs-InP multiple-quantum-well absorption region and SiO/sub 2/ of the MOSFET were directly bonded. From the experimental results, we confirmed that the light-controlled current was increased by shortening the gate length of the MOSFET, and that an 1850 A/W responsivity was obtained in a 3.5-/spl mu/m gate length device using an irradiation of 1.5-/spl mu/m wavelength light.

High-performance GaAs MESFETs with advanced LDD structure for digital, analog, and microwave applications

GaAs MESFETs with advanced LDD structure have been developed by using a single resist-layered dummy gate (SRD) process. The advanced LDD structure suppresses the short channel effects, and reduces source resistance, while maintaining a moderate breakdown voltage. The 0.3-/spl mu/m enhancement-mode devices exhibit a transconductance of 420 mS/mm, while the breakdown voltage of the depletion-mode device (V/sub th/=-500 mV) is larger than 6 V. The standard deviation of the threshold voltage for 0.3-/spl mu/m devices is less than 30 mV across a 3-in wafer. The 0.3-/spl mu/m devices exhibit an average cutoff frequency of 47.2 GHz with a standard deviation of 1.3 GHz across a 3-in wafer. The cutoff frequency of a 0.15-/spl mu/m device is as high as 72 GHz. D-type flip-flop circuits for digital IC applications and preamplifier for analog IC applications fabricated with 0.3-/spl mu/m gate length devices operate above 10 Gb/s. In addition, the 0.3-/spl mu/m devices also show good noise performance with a noise figure of 1.1 dB with associated gain of 6.5 dB at 18 GHz. These results demonstrate that GaAs MESFETs with an advanced LDD structure are quite suitable for digital, analog, microwave, and hybrid IC applications.

Characterization and profile optimization of SiGe pFETs on silicon-on-sapphire

We present the details of the fabrication, electrical characterization, and profile optimization of a SiGe pFET on silicon-on-sapphire (SOS) technology. The results show that the SiGe pFETs have higher low-field mobility (/spl mu//sub eff/), transconductance (g/sub m/), and cutoff frequency (f/sub T/) than a comparable Si pFET. At low temperature (85 K), a secondary peak is observed in the linear g/sub m/ of the SiGe pFETs and is attributed to hole confinement in the SiGe channel. The effect of reducing the SOS film thickness on the mobility and short-channel performance is studied. A low-frequency noise study shows significant improvement in the SiGe pPETs over comparable Si pFETs, and is attributed to a lower sampling of interface trap density caused by the band offset at the oxide interface due to SiGe. Drain Induced Back Channel Inversion (DIBCI) is shown to occur in short gate length devices, resulting in high off-state leakage current through conduction at the back silicon-sapphire interface. The paper also discusses important optimization issues in the design of 0.25-/spl mu/m gate length SiGe pFETs. A novel structure is proposed which optimizes the threshold voltage, maximizes hole confinement gate voltage range and cutoff frequency, while at the same time minimizing DIBCI to make the design usable to gate lengths as short as 0.25 /spl mu/m.

Metamorphic In0.52Al0.48As/In0.53Ga0.47As HEMTs on GaAs substrate with fT over 200 GHz

MBE-grown metamorphic In0.52Al0.48As/In0.53Ga0.47As HEMTs on GaAs substrates are presented. A linearly-graded InAlGaAs buffer layer is employed for strain relaxation. A mobility of 9520 cm2/Vs and a sheet density of 2.85 × 1012 cm-2 are achieved at room temperature. Devices with gate lengths ranging from 0.18 to 1.0 µm have been fabricated. Large drain currents and extrinsic transconductances with values up to 900 mA/mm and 1.1 mS/mm, respectively, are reported. For a 0.18 µm gate length device, a unity current gain cutoff frequency (fT) of 204 GHz is obtained. To the authors&apos; knowledge, this is the highest fT to date for a metamorphic HEMT on GaAs.

Si/SiGe field-effect transistors*

Over the last few years, SiGe heterodevices with outstanding rf performance have been introduced to meet the needs of modern consumer electronics, which require novel silicon-based low cost–high speed components with improved current gain, low noise, and reduced power consumption operating in the GHz range. This article reviews device and the first circuit results of lateral modulation doped SiGe modulation doped hetero-field-effect transistors (MODFETs) with Schottky gates as well as lateral and vertical SiGe metalorganic field effect transistors (MOSFETs) focusing on dc characteristics, rf performance comprising cutoff frequencies, delays, and on layer design. With an fmax, of up to 92 GHz, the highest maximum frequency of oscillation reported so far for any Si-based FET, and transconductances gme up to 470 mS/mm, the n-SiGe MODFET is presently improving in speed with combining the advantages of heterodevices with well-established Si technology. For p-SiGe MODFETs cutoff frequencies ft of 70 GHz and fmax of 84 GHz have been measured. A reduced gate leakage and an improved voltage swing is achieved using MOS-gated heterodevices. For p-channel SiGe hetero-MOSFETs room temperature transconductances up to 210 mS/mm for 0.25 μm gate-length devices have been measured. Vertical MOSFETs allow further device scaling into the deep sub-100 nm range and thus enable us to overcome performance limits due to minimum feature sizes using state-of-the-art lithography techniques.

Ga2O3(Gd2O3)/InGaAs enhancement-mode n-channel MOSFETs

We have demonstrated the first Ga/sub 2/O/sub 3/(Gd/sub 2/O/sub 3/) insulated gate n-channel enhancement-mode In/sub 0.53/Ga/sub 0.47/As MOSFET's on InP semi-insulating substrate. Ga/sub 2/O/sub 3/(Gd/sub 2/O/sub 3/) was electron beam deposited from a high purity single crystal Ga/sub 5/Gd/sub 3/O/sub 12/ source. The source and drain regions of the device were selectively implanted with Si to produce low resistance ohmic contacts. A 0.75-/spl mu/m gate length device exhibits an extrinsic transconductance of 190 mS/mm, which is an order of magnitude improvement over previously reported enhancement-mode InGaAs MISFETs. The current gain cutoff frequency, f/sub t/, and the maximum frequency of oscillation, f/sub max/, of 7 and 10 GHz were obtained, respectively, for a 0.75/spl times/100 /spl mu/m/sup 2/ gate dimension device at a gate voltage of 3 V and drain voltage of 2 V.

Optimization of submicrometre GaAs MESFET for improved performance

A theoretical and optimal model, based on a trial function approach with improved performance for submicrometre gate length devices, is proposed. This helps in predicting the deviations resulting from process parameter variations. The main physical phenomena such as field dependent mobility, overshoot velocity and carrier injection in the buffer layer are also considered. The extension of the depletion region in the ungated part of the device fully explains trans conductance compression. When calculated results from the present model are compared with available experimental data and numerically simulated results, an encouraging correspondence between the two is observed, thereby, confirming the validity of the model.