Gate-induced Drain Leakage Current Research Articles

Modeling of inner-outer gates and temperature dependent gate-induced drain leakage current of junctionless double-gate-all-around FET

In this paper, the temperature-dependent gate-induced drain leakage (GIDL) current model is proposed with the help of a lateral electric field (EL) across the inner and outer gate interfaces of the junctionless double-gate-all-around (JL-DGAA) field-effect transistor (FET). The EL at the interface is obtained from the surface potential equation after solving the 3D Poisson equation with appropriate boundary conditions. The derived model is validated using the well-calibrated TCAD simulator platform with experimental data. A higher GIDL current at the outer gate-channel interface is observed compared to the inner gate-channel interface in the OFF-state conditions due to the high EL between the channel and drain, which is reported for the first time here. The effect of temperature (from 200 K to 500 K) on the GIDL current is also observed, which increases linearly with increasing temperature. Further, the impact of induced mechanical stress (MS) is investigated on the GIDL current, where the GIDL current increases exponentially with increasing induced MS due to effective mass and band gap reduction. Finally, the dynamic performance is investigated in terms of the gate delay time as a function of channel length and temperature. The gate delay diminishes with decreasing channel length and increasing temperature, which shows the switching speed and ability of the device.

Parameteric optimization of SiGe S/D NT JLFET using analytical modeling to improve L‐BTBT induced GIDL

AbstractIn the present work, we investigate the impact of structure dimensional parameters on the short channel effects which occurs especially below 20 nm regime particularly gate induced drain leakage (GIDL) current. Using technology computer aided design simulation (TCAD), we have examined the GIDL for SiGe as source/drain in NTJLFET. The structural dimensional parameters such as the nanotube thickness, core and outer gates thickness and gate electrode work function shows the significant impact on the band to band tunneling in lateral direction (L‐BTBT) which induced GIDL current. It is analyzed that increase in the nanotube thickness and physical oxide thickness increase the GIDL current, while increasing the gate electrode work function, core gate and outer gate thicknesses gives reduced GIDL current. The SiGe S/D NTJLFET produce a remarkable high ION/IOFF ratio ~ 1011. A compact model for GIDL current is also developed which shows the dependency of structure parameters on leakage current. The SiGe has been incorporated as source and drain in NTJLFET which creates the energy band discontinuity. Furthermore, SiGe S/D NTJLFET is fairly compared with the conventional NT JLFET and nanowire (NW) JLFET and shows an improved performance.

A Novel Read Scheme Using GIDL Current to Suppress Read Disturbance in 3-D nand Flash Memories

In this paper, a novel read scheme using gate-induced drain leakage (GIDL) current is proposed to suppress read disturbance in 3-D NAND flash memories. The proposed read scheme is demonstrated through the technology computer-aided design (TCAD) simulation. In the selected string, GIDL current is not generated due to the low potential difference. On the other hand, in the unselected string, holes are accumulated under the selected cell and potential of the selected cell is enhanced due to the GIDL current before the read operation. The potential differences between the selected and adjacent cells are decreased and maximum electric field (Em) is decreased. Therefore, soft programming in the selected cell during the read operation is decreased and hot carrier injection (HCI) between selected and adjacent cells is reduced completely. The proposed read scheme can be applied to high stacked WL layers over 200 layers.

Investigating DC and AC degradation behaviors to P-type low temperature polycrystalline silicon thin film transistor with fin-like structure

Currently, thin film transistor (TFT) based on planar structure is widely used in the applications of display panels. However, when the device is scaling-down, new device structures or novel materials should be introduced. In this work, the low temperature polycrystalline silicon (LTPS) TFT with fin-like structure is investigated. On the basis of electrical measurements, the device features good switching characteristics with low operating voltages. However, the I d–V g sweeping result exhibits off-state leakage, which is known as the gate-induced drain leakage (GIDL) current. The GIDL current is increased with the drain bias and the temperature increasing. To observe the GIDL current degradations, different gate biases with negative bias stress and positive bias stress are applied. The results show different degradation behaviors. In addition, bias stresses with DC and AC methods are also applied to verify the device reliability. Both threshold voltage (V t) shift and sub-threshold swing (S.S.) are also extracted to verify the degradations of the device. Finally, the physical models are also proposed to illustrate the degradation behaviors of the LTPS device with a fin-like structure, which can be beneficial to future related development of LTPS-based devices.

Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield

TCAD simulation using Silvaco software has shown that the 3G_DFM, which has SG1 (Select Gate 1), PL (Plate Line Gate), and SG2 (Select Gate 2) between SL (Source Line) and BL (Bit Line), has a long retention time of 100ms at 85 °C, and a robust disturbance shield which is a thousand times BL stress. The two select gates SG1 and SG2 protect the recombination of holes in the FB (Floating Body) at the SL and BL pn-junctions, and shield the BL stress arising during other page operations, which leads to the GIDL (Gate Induced Drain Leakage) current.

Multi-gate BCAT Structure and Select Word-line Driver in DRAM for Reduction of GIDL

In this article, we evaluate gate induced drain leakage that affects the refresh time of buried cell array transistor DRAM cells. We proposed a multi-gate BCAT structure to minimize gate induced drain leakage and modified the select word-line circuit to operate multi-gate buried cell array transistor by adding only one PMOS. In the multi-gate structure, by changing the gate voltage, the work function of the metal gate was adjusted to effectively mitigate the electric field formed in the drain region by approximately four orders. As an adopting multi-gate structure, band to band tunneling is suppressed and gate induced drain leakage current is reduced. We verified that the dual-gate structure had less leakage current than the poly-Si BCAT using the TCAD simulation. The reduction of leakage according to the number of gates is inferred by confirming the reduction in GIDL of the three-gate structure compared with the dual-gate structure. Furthermore, the SPICE simulation confirmed that the proposed select word-line circuit transmits different optimized voltages to multiple gates when it is off than while transferring the same voltage when on. This structure can also be extended for application to other DRAM structures, such as the vertical structure and 3D-stacked DRAMs.

Impact of Process-Induced Inclined Sidewalls on Gate-Induced Drain Leakage (GIDL) Current of Nanowire GAA MOSFETs

The shape of the channel cross section in rectangular nanowire (NW) gate-all-around (GAA) MOSFETs turns trapezoidal due to process variations. In this article, the impact of process-induced inclination of sidewalls on gate-induced drain leakage (GIDL) current in the trapezoidal channel NW GAA MOSFETs has been systematically investigated using experimental and calibrated TCAD simulation results. The GIDL current has also been analyzed against the variation in other device parameters, such as channel length, height, and width. The lateral band-to-band tunneling (L-BTBT) mechanism at the channel/drain junction has been considered in simulations to obtain the GIDL current. The investigation reveals that the GIDL current increases up to two times if the process-induced sidewalls inclination angle increases from 0° to 20°.

Extension of DRAM Retention Time at 77 Kelvin by Replacing Weak Rows with Large GIDL Current

At 77 Kelvin, it was found that the weak cells with large gate-induced drain leakage current are quite localized in six weak rows out of the entire 524,288 rows of a 8 Gb DRAM chip. By replacing the six weak rows, the DRAM retention time was increased from 8 to 4096 seconds at 77 Kelvin. Because this retention time is over 64,000 times longer than the JEDEC retention-time specification of 0.064 seconds, the DRAM refresh power can be reduced to a negligible level at the data center. To achieve this, the DRAM controller was modified to find weak rows by using three different data patterns at power-on reset and a reserved row of DRAM is used when access to a weak row address occurs during the normal operation.

Multiplexed Silicon Nanowire Tunnel FET-Based Biosensors With Optimized Multi-Sensing Currents

In this study, silicon nanowire (SiNW) FET-based and SiNW tunnel FET (TFET)-based biosensors are co-integrated with CMOS circuits by using top-down approached and CMOS-compatible back-end process simultaneously. The possibility of multiplexed sensing is verified with the fabricated FET and TFET biosensors. For multiplexed-sensing, two separate sensing materials which react with two distinct bio-targets are formed by partially capping the gold on SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> film through a lift-off process. Then two bio-receptors which selectively combine to the gold and the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> are deposited. After the reaction of each biomolecule to each receptor, the changes of saturation and gate-induced-drain-leakage (GIDL) currents are monitored in the FET sensor. It is experimentally confirmed that two different biomolecules are independently detectable by the changes of the saturation and the GIDL currents in the FET sensor. To solve the dependence of the gold formation position on the sensitivity as well as the large current difference between the saturation and the GIDL currents, we demonstrated the TFET biosensor which uses the changes of tunneling and ambipolar currents generated in the source and the drain end. As a result, it is clearly revealed that two different biomolecules can be detected without interference, regardless of the position of the gold layer by the changes of the tunneling and the ambipolar currents with almost equivalent sensing current level.

Degradation modeling with spatial mapping method in low temperature poly silicon thin film transistor aged off-state bias

We conducted experimental and quantitative studies on the effects of off-state bias stress of the p-type polycrystalline silicon thin film transistors, and present a degradation model using spatial mapping simulations. In the off-state bias stress condition, the gate induced drain leakage current (GIDL) is determined by the gate and drain voltage (Vgd), and the gate bias stress above a certain bias is accompanied by a change in Vth. The spatial distributions of the electric field and the electron concentration are considered as degradation factors, and are used in the equations for defect creation (DC) and the charge trapping (CT) model. We had to implement different forms of the aging model in the two regions: 1) CT in the poly-Si/SiOX interface, and 2) DC in the channel bulk. Finally, our degradation model allows us to analyze how the GIDL current decreases with various aging conditions, and provides a quantitative relationship between the amount of charge trapping and the amount of defect creation.

Comparing bulk-Si FinFET and gate-all-around FETs for the 5 ​nm technology node

In this paper, bulk CMOS finFET, horizontal gate-all-around (GAA) nanowire and nanosheet field-effect transistors are compared for the 5 ​nm technology node. The performance of these transistors and the circuits comprising them is assessed through 3-D technology computer-aided design (TCAD) simulations and circuit level SPICE simulations of BSIM compact models calibrated to the TCAD results, respectively. Full parasitic extraction is used on standard cell and static random access (SRAM) memory cell layouts to ensure accurate delays. The target of this work is a 5 ​nm technology node follow-on to an existing 7 ​nm predictive process design kit (PDK) in common academic use. Subthreshold slope, drain induced barrier lowering, gate-induced drain leakage and subthreshold current are compared for different gate lengths. Transistor performance is also compared for various raised source/drain lengths and low-k gate spacer widths. The gate-all-around field-effect transistors show better electrostatic performance as expected. However, the simulation results show that finFET devices will be adequate at the 5 ​nm node, should the GAA devices prove to be difficult to produce in high volume manufacturing.

Physics-based analytic modeling and simulation of gate-induced drain leakage and linearity assessment in dual-metal junctionless accumulation nano-tube FET (DM-JAM-TFET)

Physics-based analytical model is proposed in this paper which analyzes the effect of temperature, channel length and silicon film radius on gate-induced drain leakages (GIDL) in dual-metal junctionless accumulation nano-tube FET (DM-JAM-TFET). Formulation and analysis for electric field, Ez, surface potential and gate-induced drain leakage current, Igidl have been done with the help of appropriate boundary conditions utilized in solving two-dimensional Poisson’s equation. Also, the effect of variation in temperatures at T = 300 K and 500 K, silicon film channel length (L 30 nm and 40 nm) and radius of R = 9 nm and R = 10 nm have been studied. The simulated results seem to be in good compliance with the analytical results. To analyze the applicability of DM-JAM-TFET for RFIC applications, linearity of the aforesaid device has been deeply investigated by comparing DM-JAM-TFET with JAM-GAA and DM-JAM-GAA at channel length, L = 20 nm. The linearity metrics namely gm1, gm2, gm3, VIP2, VIP3, IMD3 and IIP3 have been significantly improved in DM-JAM-TFET making it intermodulation distortion resistant.

Modeling of shallow extension engineered dual metal surrounding gate (SEE-DM-SG) MOSFET gate-induced drain leakage (GIDL)

In this paper, an analytical paradigm for the gate-induced drain leakage (GIDL) for shallow extension engineered dual metal surrounding gate (SEE-DM-SG) MOSFET using superposition technique with appropriate boundary conditions is proposed. Electric field, Ez, gate-induced drain leakage current, IGIDL, and surface potential have been modeled. The analytical model has been critically examined for different channel lengths, silicon film radii and temperatures. The Arrhenius plot for the gate leakages has also been modeled. The analytical results obtained have been verified with the simulated data. In addition to the analytical results, the curtailment of the band-to-band tunneling (which further reduces the leakages, in particular GIDL) by SEE-DM-SG MOSFET is deeply studied and investigated by analyzing band energy across the valence and conduction bands.

Curing of Hot-Carrier Induced Damage by Gate-Induced Drain Leakage Current in Gate-All-Around FETs

Gate oxide aging in a gate-all-around (GAA) FET fabricated on a bulk substrate was successfully cured by gate-induced drain leakage (GIDL) current. High level of GIDL current flows during the off-state cures the gate oxide aging by hot-carrier injection (HCI). The recovery behaviors were analyzed by tracing changes in the device parameters. Especially, it was found that the curing was not associated with the electric field or created holes under the bias conditions for GIDL, but was associated with the elevated temperature. The GIDL recovery requires neither extra apparatus for Joule heating nor circuit modification. This work can be useful for various FETs which have high off-state current.

Effect of OFF-State Stress on Gate-Induced Drain Leakage by Interface Traps in Buried-Gate FETs

The gate-induced drain leakage (GIDL) current is one of the major leakage sources in a dynamic random-access memory (DRAM) cell transistor. In addition to band-to-band tunneling (BTBT), which causes GIDL in the gate-to-drain overlap region, the generation of interface traps in the gate dielectric increases the GIDL current by trap-assisted two-step tunneling (TATT). In this article, the influence of OFF-state stress on the generation of the interface traps, which deteriorates GIDL, was quantitatively analyzed with charge pumping (CP) characterization method in buried-channel array transistors (BCATs) for DRAM cells. The applied stress increased the GIDL current while simultaneously degrading device performance including such as transconductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) and ON-state current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ), due to the generation of the interface traps. By using the CP characterization, the interface traps were spatially profiled along the gate-to-drain overlap region in the junction. Trap distribution inside the energy bandgap was also characterized.

Extreme Temperature Operation of Ultra-Wide Bandgap AlGaN High Electron Mobility Transistors

High Aluminum content channel (Al0.85Ga0.15N/ Al0.7Ga0.3N) High Electron Mobility Transistors (HEMTs) were operated from room temperature to 500°C in ambient. The devices exhibited only moderate reduction, 58%, in on-state forward current. Gate lag measurements at 100 kHz and 10% duty only showed a slight reduction in pulsed current from DC at 500°C and high gate voltages. Interfacial trap densities were $2 \times 10^{11}$ over the range 25–300°C and $3 \times 10^{12}$ cm $^{-2}$ from 300–500°C from the subthreshold swing. These low interfacial trap densities and the near ideal gate lag measurement indicate high-quality epi layers. The insulating properties of the barrier layer led to low gate induced drain leakage current of $\sim 10^{-12}$ A/mm and $\sim 10^{-8}$ A/mm at 25 and 500°C, respectively. Low leakage current was enabled by the high Schottky barrier of the Ni/Au gate, 1.1 eV and 3.3 eV at 25 and 500°C, respectively. These properties of the AlGaN channel HEMTs demonstrate their potential for high power and high temperature operation.

Shallow Extension Engineered Dual Material Surrounding Gate (SEE-DM-SG) MOSFET for improved gate leakages, analysis of circuit and noise performance

The leakages in off state, particularly Gate Induced Drain Leakage (GIDL) has been addressed and reduced by proposing a Shallow Extension Engineered Dual Material Surrounding Gate (SEE-DM-SG) MOSFET. The shallow extensions create an insulating layer, which acts as a diffusion stopper and thereby suppresses the off state leakages. It is done by comparing the off-state performance of SEE-DM-SG MOSFET with Dual Metal Surrounding Gate (DM-SG) MOSFET and Surrounding Gate (SG) MOSFET. GIDL current is being reduced to an order of 10−12 A. Drain Induced Barrier Lowering (DIBL) has been curtailed to a greater extent in SEE-DM-SG MOSFET when compared with DM-SG MOSFET and SG MOSFET. GIDL has been extensively investigated for different drain voltages and temperatures; in order to study their impact on it. It was so found that GIDL was minimal for SEE-DM-SG MOSFET under different bias and temperature conditions. Arrhenius plot has also been plotted and deeply investigated as it instigates the GIDL activation energy (EA). It has been so found that SEE-DM-SG MOSFET poses higher EA and thereby suggests minimal BTBT (Band To Band Tunneling). So as to enhance the device applicability for low noise amplifier, the noise performance of SEE-DM-SG MOSFET has also been deeply investigated. Noise conductance (NC) and Noise Figure (NF) have been significantly curtailed in SEE-DM-SG MOSFET over DM-SG and SG MOSFET. A CMOS inverter has also been designed using SEE-DM-SG MOSFET and the output characteristics have also been compared for the aforesaid device architectures and higher Noise Margin has been observed in SEE-DM-SG MOSFET, making it more immune to noise.

P‐6.6: Effects of lightly Doped Drain Structure in n‐channel ELA Bridged‐Grain Poly‐Si TFTs

We lead the lightly doped drain (LDD) structure into the bridged‐grain (BG) poly‐Si thin film transistor (TFT). This combined structure can restrain the gate induced drain leakage current (GIDL) and the electrical characteristics shows not much sacrifice. A high Ion/Ioff current ratio 3.79×108 is achieved. Besides, the device reliability is improved significantly. Because the lateral electrical field decreases by LDD, lower trap state density is generated in the SiO2/poly‐Si interface and the grain boundaries of poly‐Si near the surface conduction channel, resulting in the stable on‐state drive current (Ion) and drain saturation voltage (Vdsat). All test results indicate that the BG poly‐Si TFT with a LDD structure will work well and has a great potential for system‐on‐panel application.

Compact Modeling of Temperature-Dependent Gate-Induced Drain Leakage Including Low-Field Effects

We model the temperature-dependent gate-induced drain leakage (GIDL) in FinFETs. Berkeley short-channel IGFET model-common multi gate (BSIM-CMG) model for FinFET uses the only band-to-band tunneling (BTBT) to model the GIDL mechanism, which is not sufficient to capture the GIDL at low electric field. The proposed model captures trap-assisted tunneling (TAT) at low electric field and BTBT at a high electric field, in the gate–drain overlap region. It contains a single piece expression for trap-assisted tunneling GIDL current, especially present in the sub-20-nm FinFET technology node. The model is validated with the measurement data and it accurately captures the physical behavior of GIDL current. The developed model can be implemented in industry standard compact models.

Investigation of Gate Sidewall Spacer Optimization From OFF-State Leakage Current Perspective in 3-nm Node Device

In this paper, the structural and material optimization of gate sidewall spacer in the perspective of OFF-state leakage current was performed in a 3-nm node nanoplate FET (NPFET). Gate-induced drain leakage (GIDL) current, a dominant factor of OFF-state leakage current, and active performance (ON-current, ON/OFF current ratio, and dynamic performance) were co-optimized according to the structural correlation of gate sidewall spacer with other structural components such as gate, source, and drain length. By optimizing the structure for gate and spacer, intrinsic delay was improved by 9.8%, GIDL current was reduced by ~78%, and then on/off current ratio ( ${I}_{\mathrm{\scriptscriptstyle ON}}/{I}_{\mathrm{\scriptscriptstyle OFF}})$ was enhanced by 4.2 times. On-current ( ${I}_{\mathrm{\scriptscriptstyle ON}}$ ) according to contact resistance ( ${R}_{\text {con}}$ ) and dynamic performance was analyzed in relation to source/drain (S/D) and spacer. Consequently, the intrinsic delay was improved by 10% and GIDL current reduced by about 92%, which enhanced ${I}_{\mathrm{\scriptscriptstyle ON}}/{I}_{\mathrm{\scriptscriptstyle OFF}}$ by 7.9 times accordingly. Furthermore, by comparing structural relations between gate spacer and S/D spacer, a better structural optimization method was proposed.