Compact Modeling of Temperature-Dependent Gate-Induced Drain Leakage Including Low-Field Effects

Abstract

We model the temperature-dependent gate-induced drain leakage (GIDL) in FinFETs. Berkeley short-channel IGFET model-common multi gate (BSIM-CMG) model for FinFET uses the only band-to-band tunneling (BTBT) to model the GIDL mechanism, which is not sufficient to capture the GIDL at low electric field. The proposed model captures trap-assisted tunneling (TAT) at low electric field and BTBT at a high electric field, in the gate–drain overlap region. It contains a single piece expression for trap-assisted tunneling GIDL current, especially present in the sub-20-nm FinFET technology node. The model is validated with the measurement data and it accurately captures the physical behavior of GIDL current. The developed model can be implemented in industry standard compact models.