Abstract
State-of-the-art FinFETs exhibit the Gate-Induced-Drain-Leakage (GIDL) current, which cannot be attributed entirely to conventional Band-to-Band Tunneling (BTBT) physics for GIDL [1]. For the strained FinFET technology, the Trap-Assisted Tunneling (TAT) is the governing physical mechanism for most GIDL leakage due to a low gate induced vertical field in the gate-drain overlap region. This work presents the TAT-based GIDL compact model, and the developed model is validated with measurement data and TCAD simulations. The model is implemented as part of the industry-standard BSIM-CMG compact model for FinFETs.
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