Analysis of Gate-Induced Drain Leakage Mechanisms in Silicon-Germanium Channel pFET

Abstract

Silicon-germanium is an alternative channel material for pMOS FETs at 32-nm node and beyond because of lower threshold voltage and higher channel mobility in high-k metal gate technology. However, gate-induced drain leakage (GIDL) is a major concern at low power technology nodes because of band-to-band and trap-assisted tunneling (TAT) due to reduced bandgap. Here, we have studied the GIDL dependence on temperature as well as drain and substrate bias. Experimental results and Technology computer-aided design (TCAD) simulations suggest that the mechanism responsible for GIDL during off state is mostly phonon-assisted band-to-band tunneling (BTBT) in the top SiGe layer near the drain surface and is further contributed by BTBT at the drain sidewall junction. Other GIDL mechanisms such as TAT at the extension/sidewall dominate for other drain, gate, and substrate bias voltages.