Gate Electrode Research Articles

Modulating Neuromorphic Behavior of Organic Synaptic Electrolyte-Gated Transistors Through Microstructure Engineering and Potential Applications.

Organic synaptic transistors are a promising technology for advanced electronic devices with simultaneous computing and memory functions and for the application of artificial neural networks. In this study, the neuromorphic electrical characteristics of organic synaptic electrolyte-gated transistors are correlated with the microstructural and interfacial properties of the active layers. This is accomplished by utilizing a semiconducting/insulating polyblend-based pseudobilayer with embedded source and drain electrodes, referred to as PB-ESD architecture. Three variations of poly(3-hexylthiophene) (P3HT)/poly(methyl methacrylate) (PMMA) PB-ESD-based organic synaptic transistors are fabricated, each exhibiting distinct microstructures and electrical characteristics, thus serving excellent samples for exploring the critical factors influencing neuro-electrical properties. Poor microstructures of P3HT within the active layer and a flat active layer/ion-gel interface correspond to typical neuromorphic behaviors such as potentiated excitatory postsynaptic current (EPSC), paired-pulse facilitation (PPF), and short-term potentiation (STP). Conversely, superior microstructures of P3HT and a rough active layer/ion-gel interface correspond to significantly higher channel conductance and enhanced EPSC and PPF characteristics as well as long-term potentiation behavior. Such devices were further applied to the simulation of neural networks, which produced a good recognition accuracy. However, excessive PMMA penetration into the P3HT conducting channel leads to features of a depressed EPSC and paired-pulse depression, which are uncommon in organic synaptic transistors. The inclusion of a second gate electrode enables the as-prepared organic synaptic transistors to function as two-input synaptic logic gates, performing various logical operations and effectively mimicking neural modulation functions. Microstructure and interface engineering is an effective method to modulate the neuromorphic behavior of organic synaptic transistors and advance the development of bionic artificial neural networks.

Non-equilibrium transport in polymer mixed ionic-electronic conductors at ultrahigh charge densities.

Conducting polymers are mixed ionic-electronic conductors that are emerging candidates for neuromorphic computing, bioelectronics and thermoelectrics. However, fundamental aspects of their many-body correlated electron-ion transport physics remain poorly understood. Here we show that in p-type organic electrochemical transistors it is possible to remove all of the electrons from the valence band and even access deeper bands without degradation. By adding a second, field-effect gate electrode, additional electrons or holes can be injected at set doping states. Under conditions where the counterions are unable to equilibrate in response to field-induced changes in the electronic carrier density, we observe surprising, non-equilibrium transport signatures that provide unique insights into the interaction-driven formation of a frozen, soft Coulomb gap in the density of states. Our work identifies new strategies for substantially enhancing the transport properties of conducting polymers by exploiting non-equilibrium states in the coupled system of electronic charges and counterions.

Ambipolar current suppression in drain elevated TFET using a novel extended drain structure with a moderate doping profile

In this paper, a simple and compact silicon-based Elevated and Extended Drain with Hetero-Dielectric Gate Oxide TFET (EED HDGO TFET) is proposed to suppress the ambipolar current in Elevated Drain TFET (ED TFET). The proposed device structure uses a moderately doped drain with a doping concentration of ∼1018 cm−3 and a high drain length of ∼50–100 nm. The combination of the moderate drain doping profile and the extended drain length reduced the impact of the electrostatic potential from the positive voltage of the drain electrode on the channel–drain junction. This structural technique widens the tunneling width at the channel–drain region causing the tunneling current to decrease significantly. The tunneling width is further increased by structurally isolating the channel–drain junction region from the gate electrode. Thus, distancing the channel–drain junction from both the gate electric field and the static drain potential of the drain electrode causes full suppression of the ambipolar (Iamb) current. The proposed structure yields Iamb and Ioff as low as ∼10−18 A/μm and ∼10−17 A/μm respectively, while maintaining the Ion as ∼0.3 mA. The device is optimized for low power and high-speed digital circuits through intensive parametric analysis on gate–drain Cgd and the gate–source Cgs capacitances for various device parameters.

Integrated microfluidic chip with a MIP-gated organic electrochemical transistor for continuous, selective, and label-free quantification of tumor marker

Early diagnosis of cancer is crucial to effective treatment of the patients and to higher survival rates. Tumor marker detection as an effective and noninvasive cancer diagnosis method has important clinical significance. N1, N12-diacetylspermine (DAS) is a new tumor marker. The development of its detection methods is an urgent need for medical diagnosis and human health monitoring. The conventional detection methods of DAS are labor-intensive and time-consuming approaches. In this work, a novel electrochemical detection platform was established by integrating an organic electrochemical transistor (OECT) with a microfluidic chip and applied for trace measurement of DAS. The sensing unit is a gate electrode in the OECT modified with molecularly imprinted polymers (MIPs), which can be used as an artificial receptor to realize label-free detection. The high specific recognition ability of MIPs films combined with the amplified function of an OECT yielded a highly sensitive and selective electrochemical detection chip. The integrated microfluidic channel controlledthe exact amount of solution to be delivered and provided real-time detection of DAS. The experimental results indicated that changes in channel current was proportional to DAS concentrations from 1 nM to 10 μM, with the detection limits of 0.8 nM. It is the first demonstration of the integration of a microfluidic system with a MIP-gated OECT for real-time tumor marker detection. The study results of this work helped to develop Point-Of-Care (POC) tools for the early diagnosis of lung cancer, colon cancer and breast cancer.

All-Solution-Processed Electronics with Sub-Microscale Resolution and Nanoscale Fidelity Fabricated Via a Humidity-Controlled, Surface Energy-Directed Assembly Process.

Solution-based processes have received considerable attention in the fabrication of electronics and sensors owing to their merits of being low-cost, vacuum-free, and simple in equipment. However, the current solution-based processes either lack patterning capability or have low resolution (tens of micrometers) and low pattern fidelity in terms of line edge roughness (LER, several micrometers). Here, we present a surface energy-directed assembly (SEDA) process to fabricate metal oxide patterns with up to 2 orders of magnitude improvement in resolution (800 nm) and LER (16 nm). Experiment results show that high pattern fidelity can be achieved only at low relative humidities of below 30%. The reason for this phenomenon lies in negligible water condensation on the solution droplet. Employing the SEDA process, all-solution-processed metal oxide thin film transistors (TFTs) are fabricated by using indium oxide as channel layers, indium tin oxide as source/drain electrodes and gate electrodes, and aluminum oxide as gate dielectrics. TFT-based logic gate circuits, including NOT, NOR, NAND, and AND are fabricated as well, demonstrating the applicability of the SEDA process in fabricating large area functional electronics.

P/N-Type Conversion of 2D MoTe2 Controlled by Top Gate Engineering for Logic Circuits.

Two-dimensional (2D) transition-metal dichalcogenides (TMDCs) are regarded as promising materials for next-generation logic circuits. Top gate field-effect transistors (FETs) have independent gate control ability and can be fabricated directly on TMDC materials without a transfer process. Therefore, it has the merits of device reliability and complementary metal-oxide semiconductor (CMOS) process compatibility, which are demanded in practical circuit-level integration. However, the fabrication of the top gate FET involves depositing an insulating dielectric layer and a gate electrode in sequence on the TMDC channel material, which may affect the device performance. Insightfully investigating the influences of different top-gate-deposition methods on the electrical properties of the TMDC channel and further harnessing these influences to realize a homogeneous CMOS device on an identical 2D TMDC platform are with practice significance. In this work, p/n-type controllable top gate FET arrays based on 2H-MoTe2 are fabricated by using different top-gate-deposition methods. The electron-beam evaporation (EBE) of top metal gate exhibits an obvious n-doping effect on the 2H-MoTe2 channel and converts it from p-type to n-type, whereas the thermal evaporation of top gate affects little to the channel. High-resolution transmission electron microscopy (HR-TEM) analysis reveals that the high-energy metal atoms from the EBE process can penetrate through the 30 nm gate dielectric layers (including 10 nm Al2O3 seeding layer), leading to multiple atomic defects in both MoTe2 and the interface between MoTe2 and Al2O3. Furthermore, by utilizing the top gate engineering, a large-scale double-top-gate MoTe2 homogeneous CMOS inverter array is fabricated. The CMOS inverters exhibit clear logic swing, negligible hysteresis, and high device yield (∼93%), indicating high device reliability and stability. Notably, the fabrication process is facile, free from transfer procedure, and compatible with traditional silicon technology. This work promotes the application of 2D TMDCs in nanoelectronics integration.

A nanoscale photonic thermal transistor for sub-second heat flow switching

Control of heat flow is critical for thermal logic devices and thermal management and has been explored theoretically. However, experimental progress on active control of heat flow has been limited. Here, we describe a nanoscale radiative thermal transistor that comprises of a hot source and a cold drain (both are ~250 nm-thick silicon nitride membranes), which are analogous to the source and drain electrodes of a transistor. The source and drain are in close proximity to a vanadium oxide (VOx)-based planar gate electrode, whose dielectric properties can be adjusted by changing its temperature. We demonstrate that when the gate is located close ( < ~1 µm) to the source-drain device and undergoes a metal-insulator transition, the radiative heat transfer between the source and drain can be changed by a factor of three. More importantly, our nanomembrane-based thermal transistor features fast switching times ( ~ 500 ms as opposed to minutes for past three-terminal thermal transistors) due to its small thermal mass. Our experiments are supported by detailed calculations that highlight the mechanism of thermal modulation. We anticipate that the advances reported here will open new opportunities for designing thermal circuits or thermal logic devices for advanced thermal management.

Electrolyte gating using ionic crystals: demonstration of iontronics with ionic crystals

We perform electrolyte gating using ionic crystals instead of conventional ionic liquids and gels. By applying a gate voltage and heating the ionic crystal to a liquid state, Fermi level tuning of a carbon nanotube (CNT) film was achieved. Subsequent resolidification at room temperature ensured a fixed ion distribution in the electric double layer at the tuned state. The CNT film maintained the tuned Fermi level for over 30 days, even after the gate electrode was removed. This addresses the challenges associated with handling conventional ionic liquids and is poised to revolutionize the field of electrolyte gating for nanomaterial devices.

Toward human-like adaptability in robotics through a retention-engineered synaptic control system.

Although advanced robots can adeptly mimic human movement and aesthetics, they are still unable to adapt or evolve in response to external experiences. To address this limitation, we propose an innovative approach that uses parallel-processable retention-engineered synaptic devices in the control system. This approach aims to simulate a human-like learning system without necessitating complex computational systems. The retention properties of the synaptic devices were modulated by adjusting the amount of Ag/AgCl ink sprayed. This changed the voltage drop across the interface between the gate electrode and the electrolyte. Furthermore, the unrestricted movement of ions in the electrolyte enhanced the signal multiplexing capability of the ion gel, enabling device-level parallel processing. By integrating the unique characteristics of the synaptic devices with actuators, we successfully emulated a human-like workout process that includes feedback between acute and chronic responses. The proposed control system offers an innovative approach to reducing system complexity and achieving a human-like learning system in the field of biomimicry.

Strain-Sensor-In-Pixel Technology for Resolution-Sustainable Stretchable Displays.

One of the limitations of stretchable displays is the severe degradation of resolution or the decrease in the number of pixels per unit area when stretched. Hence, we suggest a strain-sensor-in-pixel (S-SIP) system through the adoption of hidden pixels that are activated only during the stretch mode for maintaining the density of on-state pixels. For the S-SIP system, the gate and source electrodes of InGaZnO thin-film transistors (TFTs) in an existing pixel are connected to a resistive strain sensor through the facile and selective deposition of silver nanowires (AgNWs) via electrohydrodynamic-jet-printing. With this approach, the strain sensor integrated TFT functions as a strain-triggered switch, which responds only to stretching along the designated axes by finely tuning the orientation and cycles of AgNW printing. The strain sensor-integrated TFT remains in an off-state when unstretched and switches to an on-state when stretched, exhibiting a large negative gauge factor of -1.1 × 1010 and a superior mechanical stability enduring 6000 cycles, which enables the efficient structure to operate hidden pixels without requiring additional signal processing. Furthermore, the stable operation of the S-SIP in a 5 × 5-pixel array is demonstrated via circuit simulation, implying the outstanding applicability and process compatibility to the conventional active-matrix display backplanes.

Contact‐Engineering of Self‐Aligned‐Gate Metal Oxide Transistors Processed via Electrode Self‐Delamination and Rapid Photonic Curing

AbstractMetal oxide thin‐film transistors (TFTs) offer remarkable opportunities for applications in emerging transparent and flexible microelectronics. Unfortunately, their performance is hindered by limitations associated with parasitic effects, such as parasitic electrode overlap capacitances and high contact resistance, which can severely limit their dynamic behavior. Here, an innovative method is reported to fabricate coplanar self‐aligned‐gate (SAG) indium‐gallium‐zinc‐oxide (IGZO) transistors with engineered source/drain contacts. The manufacturing process starts with the deposition and patterning of a gate electrode/dielectric stack and its functionalization with an organic self‐assembled monolayer (SAM) as the surface energy modifier. A second gold (Au) electrode is subsequently deposited over the gate electrode stack. The overlapping region between the two electrodes is removed via self‐delamination under mild sonication, forming perfectly aligned coplanar Au‐Gate‐Au electrodes. Device fabrication is completed with the spin coating of the IGZO precursor, followed by rapid photonic curing. Replacing the gold source/drain contact with bimetallic electrodes such as Au/In and Au/ITO enables a reduction in contact resistance and improves the transistor performance remarkably without increasing manufacturing complexity. The method is highly scalable, robust, and applicable to other semiconductor materials.

14‐3: Late‐News Paper: Channel Etched Coplanar TFTs for Applying a‐IGZO to High‐resolution and IT Applications

Self‐aligned a‐IGZO coplanar TFTs have high mobility, excellent large‐area uniformity, and are structurally free of parasitic caps. Accordingly, it is being adopted and mass‐produced as the backplane of OLED TV. Currently, the scope of application of OLED displays using oxide TFT backplanes is expanding to high‐resolution monitors for gaming. With this expansion, not only the size of the TFT but also its storage capacity has become an important factor in terms of aperture ratio. Instead of using a thick Passivation (PAS) Layer for storage capacity, we developed a structure that maximizes the aperture ratio by using a thin gate insulator (GI). However, GI capacitance must be used as the gate electrode and active layer electrode, but in self‐aligned coplanar structure, the active layer overlapping the gate metal is not conductive. To solve this problem, we succeeded in developing a 27‐inch QHD OLED monitor product for gaming by applying a self‐aligned coplanar structure/process that allows the active layer to simultaneously configure channels and wiring, and controlling degradation of channel characteristics.

P‐32: Dual Gate Amorphous Silicon Thin Film Transistor Technology for High Brightness and High Frame Rate Outdoor Display Panels

In this paper, we present the development of a dual‐gate (DG) architecture for hydrogenated amorphous silicon thin film transistors (a‐Si:H TFTs). The aim is to address the challenges of low on‐state current (Ion) and light‐induced degradation in traditional single‐gate (SG) TFTs. The experimental results demonstrate that the DG‐TFT exhibits significantly higher Ion compared to the SG‐TFT, and the improvement depends on the thickness of the top gate insulator. Additionally, the threshold voltage (Vth) can be adjusted by applying the top gate voltage, allowing for a full‐ swing modulation coefficient of approximately 0.2. To ensure long‐term stability, a light‐blocking layer has been incorporated as the top gate electrode, enabling the DG‐ TFT to maintain its initial properties even under intense illumination conditions of up to 28,000 nits.

Interfacial Charge Transport Enhancement of Liquid-Crystalline Polymer Transistors Enabled by Ionic Polyurethane Dielectric.

In organic field-effect transistors (OFETs) using disordered organic semiconductors, interface traps that hinder efficient charge transport, stability, anddevice performance are inevitable. Benchmark poly(9,9-dioctylfuorene-co-bithiophene) (F8T2) liquid-crystalline polymer semiconductor has been extensively investigated for organic electronic devices due to its promising combination of charge transport and light emission properties. This study demonstrates that high-capacitance single-layered ionic polyurethane (PU) dielectrics enable enhanced charge transport in F8T2 OFETs. The ionic PU dielectrics are composed of a mild blending of PU ionogel and PU solution, thereby forming a solid-state film with robust interfacial characteristics with semiconductor layer and gate electrode in OFETs and measuring high capacitance values above 10 µF cm-2 owing to the combined dipole polarization and electric double layer formation. The optimized fabricated ionic PU-gated OFETs exhibit a low-voltage operation at -3V with a remarkable hole mobility of over 5 cm2 V-1 s-1 (average = 2.50 ± 1.18 cm2 V-1 s-1), which is the highest mobility achieved so far for liquid-crystalline F8T2 OFETs. This device also provides excellent bias-stable characteristics in ambient air, exhibiting a negligible threshold voltage shift of -0.03V in the transfer curves after extended bias stress, with a reduced trap density.

Reducing Off-State and Leakage Currents by Dielectric Permittivity-Graded Stacked Gate Oxides on Trigate FinFETs: A TCAD Study.

Since its invention in the 1960s, one of the most significant evolutions of metal-oxide semiconductor field effect transistors (MOSFETs) would be the 3D version that makes the semiconducting channel vertically wrapped by conformal gate electrodes, also recognized as FinFET. During recent decades, the width of fin (Wfin) and the neighboring gate oxide width (tox) in FinFETs has shrunk from about 150 nm to a few nanometers. However, both widths seem to have been leveling off in recent years, owing to the limitation of lithography precision. Here, we show that by adapting the Penn model and Maxwell-Garnett mixing formula for a dielectric constant (κ) calculation for nanolaminate structures, FinFETs with two- and three-stage κ-graded stacked combinations of gate dielectrics with SiO2, Si3N4, Al2O3, HfO2, La2O3, and TiO2 perform better against the same structures with their single-layer dielectrics counterparts. Based on this, FinFETs simulated with κ-graded gate oxides achieved an off-state drain current (IOFF) reduced down to 6.45 × 10-15 A for the Al2O3: TiO2 combination and a gate leakage current (IG) reaching down to 2.04 × 10-11 A for the Al2O3: HfO2: La2O3 combination. While our findings push the individual dielectric laminates to the sub 1 nm limit, the effects of dielectric permittivity matching and κ-grading for gate oxides remain to have the potential to shed light on the next generation of nanoelectronics for higher integration and lower power consumption opportunities.

Overlapping top gate electrodes based on low temperature atomic layer deposition for nanoscale ambipolar lateral junctions

We present overlapping top gate electrodes for the formation of gate defined lateral junctions in semiconducting layers as an alternative to the back gate/top gate combination and to the split gate configuration. The optical lithography microfabrication of the overlapping top gates is based on multiple layers of low-temperature atomic layer deposited hafnium oxide, which acts as a gate dielectric and as a robust insulating layer between two overlapping gate electrodes exhibiting a large dielectric breakdown field of >1×109V m−1 . The advantage of overlapping gates over the split gate approach is confirmed in model calculations of the electrostatics of the gate stack. The overlapping gate process is applied to Hall bar devices of mercury telluride in order to study the interaction of different quantum Hall states in the nn′, np, pn and pp′ regime.

Enhancement-Mode Carbon Nanotube Optoelectronic Synaptic Transistors with Large and Controllable Threshold Voltage Modulation Window for Broadband Flexible Vision Systems.

The development of large-scale integration of optoelectronic neuromorphic devices with ultralow power consumption and broadband responses is essential for high-performance bionics vision systems. In this work, we developed a strategy to construct large-scale (40 × 30) enhancement-mode carbon nanotube optoelectronic synaptic transistors with ultralow power consumption (33.9 aJ per pulse) and broadband responses (from 365 to 620 nm) using low-work function yttrium (Y)-gate electrodes and the mixture of eco-friendly photosensitive Ag2S quantum dots (QDs) and ionic liquids (ILs)-cross-linking-poly(4-vinylphenol) (PVP) (ILs-c-PVP) as the dielectric layers. Solution-processable carbon nanotube thin-film transistors (TFTs) showed enhancement-mode characteristics with the wide and controllable threshold voltage window (-1 V∼0 V) owing to use of the low-work-function Y-gate electrodes. It is noted that carbon nanotube optoelectronic synaptic transistors exhibited high on/off ratios (>106), small hysteresis and low operating voltage (≤2 V), and enhancement mode even under the illumination of ultraviolet (UV, 365 nm), blue (450 nm), and green (550 nm) to red (620 nm) pulse lights when introducing eco-friendly Ag2S QDs in dielectric layers, demonstrating that they have the strong fault-tolerant ability for the threshold voltage drifts caused by various manufacturing scenarios. Furthermore, some important bionic functions including a high paired pulse facilitation index (PPF index, up to 290%), learning and memory function with the long duration (200 s), and rapid recovery (2 s). Pavlov's dog experiment (retention time up to 20 min) and visual memory forgetting experiments (the duration of high current for 180 s) are also demonstrated. Significantly, the optoelectronic synaptic transistors can be used to simulate the adaptive process of vision in varying light conditions, and we demonstrated the dynamic transition of light adaptation to dark adaptation based on light-induced conditional behavior. This work undoubtedly provides valuable insights for the future development of artificial vision systems.

Analysis on charge-retention characteristics of sub-threshold synaptic IGZO thin-film transistors with defective gate oxides

We provide a quantitative analysis on the charge-retention characteristics of sub-threshold operating In–Ga–Zn–O (IGZO) thin-film transistors (TFTs) with a defective gate-oxide for low-power synaptic applications. Here, a defective SiO2 is incorporated as the synaptic gate-oxide in the fabricated IGZO TFTs, where a defect is physically playing the role as an electron trap. With this synaptic TFT, positive programming pulses for the electron trapping are applied to the gate electrode, followed by monitoring the retention characteristics as a function of time. And this set of the programming and retention-monitoring experiments is repeated in several times for accumulating effects of pre-synaptic stimulations. Due to these accumulated stimulations, electrons are expected to be getting occupied within a deeper trap-state with a higher activation energy, which can lead to a longer retention. To verify these phenomena, a stretched exponential function and respective inverse Laplace transform are employed to precisely estimate a retention time and trap activation-energy for transient experimental results.

Organic Mixed Ionic Electronic Conductor Nanochannels for Vertical Electrochemical and Ionic Transistors

AbstractThin films of organic mixed ionic electronic conductors (OMIECs) constitute the functional layer in organic electrochemical transistors (OECTs), organic bioelectronic transducers and other ionic‐electronic devices. The thin‐film configuration constrains devices to be fabricated on impermeable substrates in the form of 2D microstructures with lateral electrodes to drive an electronic current through the thin film. In order to alleviate such constraints, novel OMIEC deposition methods are needed that produce alternatives to thin‐film devices and that are compatible with permeable substrates and electronic transport in the vertical direction. Here OMIECs filled nanoporous membranes are introduced as functional layer in devices with mixed ionic electronic transport. Electropolymerization of ethylenedioxythiophene (EDOT) monomers is used to fabricate OMIEC filled nanochannels. Electronic and ionic transport through such nanochannels are investigated and modulation of electronic as well as ionic carrier density by action of a third gate electrode is demonstrated. The novel OMIEC nanochannels enable the fabrication of vertical OECTs with high transconductance and organic ionic transistors using only additive fabrication methods.

High-sensitivity and energy-efficient chloride ion sensors based on flexible printed carbon nanotube thin-film transistors for wearable electronics

The advent of flexible single-walled carbon nanotube thin-film transistors (SWCNT-TFTs) has transformed electronics, providing significant benefits like low operating voltage, reduced power consumption, cost-effectiveness, and improved signal amplification. This study focuses on leveraging these attributes to develop a novel flexible high-sensitivity and energy-efficient chloride ion sensors based on printed flexible SWCNT-TFTs utilizing polymers-sorted semiconducting SWCNTs (sc-SWCNTs) as the active layers and ion liquids-poly(4-vinylphenol as dielectric layers along with the evaporated deposition of aluminum electrodes and printed silver electrodes as the gate and source-drain electrodes, respectively. The sensors exhibit several operational advantages, including low voltage requirements (≤1 V), rapid response speed (5.32 s), significant signal amplification (Up to 702.6 %), low power consumption (0.31 μJ at 1 mmol chloride ion), good repeatability, high sensitivity for both low and high concentrations of chloride ion (up to 100 mmol/L) and excellent mechanical flexibility (No obvious changes after bending for 10,000 times with a 5 mm radius). The detection mechanism of chloride ions was analyzed using X-ray Photoelectron Spectroscopy (XPS). It was found that chloride ions react with silver nanoparticles (AgNPs) to form silver chloride (AgCl) on printed electrodes, impeding carrier transport and reducing the currents in SWCNT TFTs. Importantly, our sensors' compatibility with smart devices allows for real-time monitoring of chloride ion levels in human sweat, offering significant potential for daily health monitoring.