Ambipolar current suppression in drain elevated TFET using a novel extended drain structure with a moderate doping profile

Abstract

In this paper, a simple and compact silicon-based Elevated and Extended Drain with Hetero-Dielectric Gate Oxide TFET (EED HDGO TFET) is proposed to suppress the ambipolar current in Elevated Drain TFET (ED TFET). The proposed device structure uses a moderately doped drain with a doping concentration of ∼1018 cm−3 and a high drain length of ∼50–100 nm. The combination of the moderate drain doping profile and the extended drain length reduced the impact of the electrostatic potential from the positive voltage of the drain electrode on the channel–drain junction. This structural technique widens the tunneling width at the channel–drain region causing the tunneling current to decrease significantly. The tunneling width is further increased by structurally isolating the channel–drain junction region from the gate electrode. Thus, distancing the channel–drain junction from both the gate electric field and the static drain potential of the drain electrode causes full suppression of the ambipolar (Iamb) current. The proposed structure yields Iamb and Ioff as low as ∼10−18 A/μm and ∼10−17 A/μm respectively, while maintaining the Ion as ∼0.3 mA. The device is optimized for low power and high-speed digital circuits through intensive parametric analysis on gate–drain Cgd and the gate–source Cgs capacitances for various device parameters.