Gate Edge Roughness Research Articles

Compact Modeling of Process Variations in Nanosheet Complementary FET (CFET) and Circuit Performance Predictions

In this work, a semi-analytical compact model of random process fluctuations in nanosheet (NS) gate-all-around (GAA) complementary FET (CFET) is proposed, including work-function variation (WFV), line edge roughness (LER), and gate edge roughness (GER). Different from the conventional NS GAA FET, GER has a significantly different impact on NS GAA CFET, due to the additional p-type work-function (p-WF) liner for p-FET threshold voltage tuning as well as the common metal gate, and a negative correlation with p-WF thickness is introduced into GER model. The proposed model is embedded into Berkeley short-channel insulated-gate field-effect transistor model-common multi-gate (BSIM-CMG) to predict the device performance variability by HSPICE Monte Carlo (MC) simulations. Excellent agreement between stochastic TCAD and HSPICE MC simulations is demonstrated. The effect of process variations on the power-performance-area (PPA) of standard cells (SDCs) and ring oscillator (RO) circuit is predicted by the proposed model. Most of the process variations make a more than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 10% to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula> 20% change in power consumption in NOR2. WFV has the greatest impact on RO PPA, making a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 10% to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula> 12.3% change in power consumption. The proposed model provides a helpful guideline for the random variation-aware CFET circuit design and related technology process development.

Impact of Process Variation on Nanosheet Gate-All-Around Complementary FET (CFET)

In this work, dc characteristic variations of nanosheet (NS) gate-all-around (GAA) complementary FET (CFET) induced by process fluctuations are investigated for the first time. Four process variability sources including work-function variation (WFV), line edge roughness (LER), gate edge roughness (GER), and random dopant fluctuation (RDF) are characterized. Compared to the conventional NA GAA FET, the differences mainly exist in GER. The electrostatic potential variation induced by GER in CFET is affected by both the common metal gate and the additional p-type work-function (p-WF) liner for p-FET. Therefore, the impact of GER on p-FET is much larger than n-FET as well as conventional NS GAA FET. Thickening the p-WF liner is proposed to overcome the drawback. Calculated overall variations considering all process fluctuation sources are also discussed, highlighting the impact of the dual-WF gate on p-FET. The results are helpful for the characterization and optimization of variations in CFET and precise CFET-based circuit design.

Impact of Process Fluctuations on RF Small-Signal Parameter of Gate-All-Around Nanosheet Transistor Beyond 3 nm Node

In the present work, the variations of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RF</i> small-signal model parameters induced by the intrinsic process fluctuations are investigated in gate-all-around (GAA) nanosheet transistor beyond 3 nm node. With the help of nonlinear rational function fitting, the RF small-signal model parameters are first analytically extracted from the non-quasi-static (NQS) equivalent circuit. The impact of work-function variation (WFV), line edge roughness (LER), and gate edge roughness (GER) on small-signal model parameters are evaluated by 3-D TCAD simulation. Results demonstrate that the channel distribution resistance <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {gdi}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {gsi}}$ </tex-math></inline-formula> are the most sensitive parameters to intrinsic process fluctuations. Furthermore, compared to LER and GER, WFV is found to have the dominated role in the variation of RF small-signal parameters, while LER and GER played a positive promotion role in aggravating the variation. The underlying physical mechanisms are discussed in detail.

Simulations of Statistical Variability in n-Type FinFET, Nanowire, and Nanosheet FETs

Four sources of variability, metal grain granularity (MGG), line-edge roughness (LER), gate-edge roughness (GER), and random discrete dopants (RDD), affecting the performance of state-of-the-art FinFET, nanosheet (NS), and nanowire (NW) FETs, are analysed via our in-house 3D finite-element drift-diffusion/Monte Carlo simulator that includes 2D Schrödinger equation quantum corrections. The MGG and LER are the sources of variability that influence device performance of the three multi-gate architectures the most. The FinFET and the NS FET are similarly affected by the MGG variations with threshold voltage and on-current standard deviations significantly lower (at least 20 %) than those of the NW FET. The LER variability has a negligible influence in the NS FET performance with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma ~{V}_{T}$ </tex-math></inline-formula> values around 12 and 42 times lower than those of the FinFET and the NW FET. The three architectures are equally affected by the RDD ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma {V}_{T}$ </tex-math></inline-formula> = 8 mV) and minimally influenced by the GER ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma {V}_{T} \approx 4$ </tex-math></inline-formula> mV). The variability of NS FETs makes them strong candidates to replace FinFETs.

Analysis on Three‐Dimensional Gate Edge Roughness of Gate‐All‐Around Devices

As the physical size of metal-oxide-semiconductor field effect transistor approaches the end of scaling down, the effect of process-induced variations such as gate edge roughness on device performance cannot be neglected. For gate-all-around devices, the three-dimensional gate profiles make the evaluation of gate edge roughness different and more complicated than that in planar metal-oxide-semiconductor field effect transistors. In this work, an evaluation algorithm was proposed to model the three-dimensional gate edge roughness in a real gate-all-around device. The results show that the typical trapezoidal gate is more likely to suffer from gate edge roughness effect than the ideal rectangular gate. The effect of the size of the gate and the correlation coefficient of the edges on the effective channel length variation was also studied.

Impact of Process Fluctuations on Reconfigurable Silicon Nanowire Transistor

In this article, the impact of intrinsic process fluctuations on reconfigurable field-effect transistor (RFET) is investigated for the first time. Three kinds of process fluctuation sources, including line edge roughness (LER), gate edge roughness (GER), and work-function variation (WFV), are performed in RFET using MATLAB and 3-D TCAD. The variation of ON-state current ${I}_{ \mathrm{\scriptscriptstyle ON}}$ due to LER presents a weak correlation with that of OFF-state current ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ . Performance variation caused by GER is mainly attributed to the control GER. WFV in control gate and source dominates the variations of ON-state characteristics. The total overall performance fluctuations are primarily attributed to WFV. In the sight of ${I}_{ \mathrm{\scriptscriptstyle ON}}$ , WFV contributed up to 84.7% and 82.8% of the total fluctuations for n- and p-type, respectively.

Does the Threshold Voltage Extraction Method Affect Device Variability?

The gate-all-around nanowire FET (GAA NW FET) is one of the most promising architectures for the next generation of transistors as it provides better performance than current mass-produced FinFETs, but it has been proven to be strongly affected by variability. For this reason, it is essential to be able to characterize device performance which is done by extracting the figures of merit (FoM) using data from the IV curve. In this work, we use numerical simulations to evaluate the effect of the threshold voltage ( $\mathrm {V_{TH}}$ ) extraction method on the variability estimation for a gate-all-around nanowire FET. For that, we analyse the impact of four sources of variability: gate edge roughness (GER), line edge roughness (LER), metal grain granularity (MGG) and random discrete dopants (RDD). We have considered five different extraction methods: the second derivative (SD), constant current (CC), linear extrapolation (LE), third derivative (TD) and transconductance-to-current-ratio (TCR). For the ideal non-deformed device at high drain bias, the effect of the extraction technique can lead to a 137 mV difference in $\mathrm {V_{TH}}$ and an 89 mV/V difference in the drain-induced-barrier-lowering (DIBL), and when considering GER and LER variability, the influence of the extraction method leads to differences in the standard deviation values of the $\mathrm {V_{TH}}$ distribution ( $\sigma \mathrm {V_{TH}}$ ) of up to 2.3 and 3.7 mV respectively, values comparable to intrinsic parameter variations. Therefore, the $\mathrm {V_{TH}}$ extraction technique presents itself as an additional parameter that should be included in performance comparisons as it can heavily impact the results.

A Multi-Method Simulation Toolbox to Study Performance and Variability of Nanowire FETs.

An in-house-built three-dimensional multi-method semi-classical/classical toolbox has been developed to characterise the performance, scalability, and variability of state-of-the-art semiconductor devices. To demonstrate capabilities of the toolbox, a 10 nm gate length Si gate-all-around field-effect transistor is selected as a benchmark device. The device exhibits an off-current () of A/m, and an on-current () of 1770 A/m, with the ratio , a value larger than that of a nm gate length Si FinFET. The device SS is 71 mV/dec, no far from the ideal limit of 60 mV/dec. The threshold voltage standard deviation due to statistical combination of four sources of variability (line- and gate-edge roughness, metal grain granularity, and random dopants) is mV, a value noticeably larger than that of the equivalent FinFET (30 mV). Finally, using a fluctuation sensitivity map, we establish which regions of the device are the most sensitive to the line-edge roughness and the metal grain granularity variability effects. The on-current of the device is strongly affected by any line-edge roughness taking place near the source-gate junction or by metal grains localised between the middle of the gate and the proximity of the gate-source junction.

Impact of Gate Edge Roughness Variability on FinFET and Gate-All-Around Nanowire FET

The effect of gate edge roughness (GER) in the sub-threshold region is studied for two state-of-the-art architectures: a 10.7-nm Si FinFET and a 10-nm Si gate-all-around (GAA) nanowire (NW) FET using an in-house 3D quantum-corrected drift-diffusion simulation tool. The GER is applied to the device gate using the characteristic values of root-mean-square amplitude and correlation length (CL). The GER-induced variability results in a standard deviation ( $\sigma $ ) for the threshold voltage ( $\textsf {V}_{\textsf {T}}$ ) of 7 mV for the FinFET when CL/Gate Perimeter = 0.66 and RMS = 0.80 nm, which is 20% greater than that of the GAA NW FET. GER is a less damaging source of variability than metal grain granularity (MGG), line edge roughness (LER), and random dopants (RD) for both devices. When compared to LER variations, $\sigma \textsf {V}_{\textsf {T}}$ due to the GER is 62% and 86% lower for the FinFET and GAA NW FET, respectively. However, although GER affects the FinFET more than the GAA NW FET, the combined variability effect of GER, MGG, LER, and RD ( $\sigma \textsf {V}_{\textsf T, comb}$ ) on the FinFET is 30 mV, a value approximately 50% smaller than that of the GAA NW FET.

Extraction of Process Variation Parameters in FinFET Technology Based on Compact Modeling and Characterization

A parameter extraction methodology of statistical process variations in FinFET is presented in this paper. First, the main impacts of various variation sources are decomposed, with detailed discussion on the correlation between threshold voltage and subthreshold swing. Second, following the Fin-edge roughness (FER) and gate-edge roughness (GER) compact models, the physical parameters, autocorrelation length and amplitude of root mean square of FER and GER, are extracted based on our proposed extraction procedure. Given a set of I-V (whether from TCAD or measured silicon data), this method can simply extract the process variation parameters from several experimental sets, such as experiments under different device geometries and/or bias conditions. With the extracted parameters integrated into compact models, the figure of merits of simulation program with integrated circuit emphasis results are well consistent with experimental measurements. The proposed methodology is not only helpful for model-based design-technology co-optimization, but also helpful for variation-aware circuit design.

Impacts of Diameter and Ge Content Variation on the Performance of Si1-xGex p-Channel Gate-All-Around Nanowire Transistors

In this work, the impacts of both nanowire diameter (DNW) and Ge content (%) on the performance of Si1−xGex Gate-all-around nanowire p -channel FETs are investigated. The variations in SiGe Gate-all-around nanowire p -channel FETs induced by DNW variation, Ge content variation, and some stochastic process variations including random dopants fluctuation, gate edge roughness, and metal gate granularity are also evaluated.

Statistical Variability and Reliability and the Impact on Corresponding 6T-SRAM Cell Design for a 14-nm Node SOI FinFET Technology

This paper presents an evaluation of 14-nm SOI FinFET CMOS SRAM codesign techniques in the presence of statistical variability and reliability impact. As statistical variability sources random discrete dopants, gate-edge roughness, fi-edge roughness, metal-gate granularity and random interface trapped charges in N/PBTI are considered.