Does the Threshold Voltage Extraction Method Affect Device Variability?

Abstract

The gate-all-around nanowire FET (GAA NW FET) is one of the most promising architectures for the next generation of transistors as it provides better performance than current mass-produced FinFETs, but it has been proven to be strongly affected by variability. For this reason, it is essential to be able to characterize device performance which is done by extracting the figures of merit (FoM) using data from the IV curve. In this work, we use numerical simulations to evaluate the effect of the threshold voltage ( $\mathrm {V_{TH}}$ ) extraction method on the variability estimation for a gate-all-around nanowire FET. For that, we analyse the impact of four sources of variability: gate edge roughness (GER), line edge roughness (LER), metal grain granularity (MGG) and random discrete dopants (RDD). We have considered five different extraction methods: the second derivative (SD), constant current (CC), linear extrapolation (LE), third derivative (TD) and transconductance-to-current-ratio (TCR). For the ideal non-deformed device at high drain bias, the effect of the extraction technique can lead to a 137 mV difference in $\mathrm {V_{TH}}$ and an 89 mV/V difference in the drain-induced-barrier-lowering (DIBL), and when considering GER and LER variability, the influence of the extraction method leads to differences in the standard deviation values of the $\mathrm {V_{TH}}$ distribution ( $\sigma \mathrm {V_{TH}}$ ) of up to 2.3 and 3.7 mV respectively, values comparable to intrinsic parameter variations. Therefore, the $\mathrm {V_{TH}}$ extraction technique presents itself as an additional parameter that should be included in performance comparisons as it can heavily impact the results.