Abstract
An in-house-built three-dimensional multi-method semi-classical/classical toolbox has been developed to characterise the performance, scalability, and variability of state-of-the-art semiconductor devices. To demonstrate capabilities of the toolbox, a 10 nm gate length Si gate-all-around field-effect transistor is selected as a benchmark device. The device exhibits an off-current () of A/m, and an on-current () of 1770 A/m, with the ratio , a value larger than that of a nm gate length Si FinFET. The device SS is 71 mV/dec, no far from the ideal limit of 60 mV/dec. The threshold voltage standard deviation due to statistical combination of four sources of variability (line- and gate-edge roughness, metal grain granularity, and random dopants) is mV, a value noticeably larger than that of the equivalent FinFET (30 mV). Finally, using a fluctuation sensitivity map, we establish which regions of the device are the most sensitive to the line-edge roughness and the metal grain granularity variability effects. The on-current of the device is strongly affected by any line-edge roughness taking place near the source-gate junction or by metal grains localised between the middle of the gate and the proximity of the gate-source junction.
Highlights
Gate-all-around nanowire field-effect transistors (GAA-NW FETs) are one of the main contenders for future CMOS technologies [1] since they provide a better electrostatic control of the channel when compared to fin field-effect transistors (FinFETs) [2], the current architecture adopted by the semiconductor industry
The Fluctuation Sensitivity Map (FSM) approach [47,48] is a methodology that we developed to predict the impact of the variability sources
This larger threshold voltage variability indicates that the variability effects may be another limiting factor for the adoption of the GAA-NW FETs in the future technological nodes
Summary
Natalia Seoane 1, * , Daniel Nagy 1 , Guillermo Indalecio 1 , Gabriel Espiñeira 1 , Karol Kalna 2 and Antonio García-Loureiro 1. Nanoelectronic Devices Computational Group, College of Engineering, Swansea University, Swansea, Wales SA1 8EN, UK
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