Gate Dielectric Material Research Articles

Ultrathin Transistors and Circuits for Conformable Electronics.

Adapting electronics to perfectly conform to nonplanar and rough surfaces, such as human skin, is a challenging task, which could open up new applications in fields of high economic and scientific interest, ranging from health to robotics, human-machine interface, and Internet of Things. The key to success lies in defining a technology that can lead to ultrathin devices, exploiting ultimately thin materials, with high mechanical flexibility and excellent electrical properties. Here, we report a hybrid approach for the development of high-performance, ultrathin and conformable electronic devices, based on the integration of semiconducting transition metal dichalcogenides, i.e., MoS2, with organic gate dielectric material, i.e., polyvinyl formal (PVF) combined with inkjet printed PEDOT:PSS electrodes. Through this novel approach, transistors and simple digital and analogue circuits are fabricated by a sequential stacking of ultrathin (nanometer) layers on a few micrometers thick polyimide substrate, which guarantees the high flexibility mandatory for the targeted applications.

Investigation of the Electrical Characteristics of AlGaN/AlN/GaN Heterostructure MOS-HEMTs with TiO2 High-k Gate Insulator

This paper investigates the impact of TiO2 high-k gate insulator on the electrical characteristics of AlGaN/AlN/GaN MOS-HEMT transistors using MATLAB and Atlas-TCAD simulation software. The physical analytical model of the MOS-HEMTs is used for simulation from Al2O3, HfO2, and TiO2 as the gate dielectric materials, which provide higher performance and reliability of the MOS-HEMT devices. The device shows a good improvement in its result of the DC and AC characteristics with different permittivity of insulator materials. Thus, the DC and AC performance of GaN MOS-HEMTs is higher than with other insulators, such as Al2O3 and HfO2 by using TiO2 as the gate dielectric. Moreover, the simulation results proved that TiO2 is the better gate dielectric material to enhance the electrical reliability of the power switching devices for high-temperature applications such as electric automobiles.

Label-free biomolecule detection with dielectrically modulated double gate single cavity InGaAs/GaAsSb HTFET: Design considerations and performance evaluation

Dielectrically Modulated Double Gate Single Cavity InGaAs/GaAsSb HTFET (DMDG–SC–InGaAs/GaAsSb HTFET) is a novel label-free, nanocavity embedded dielectrically modulated heterostructure TFET-based biosensor. The III-V heterostructure (InGaAs/GaAsSb) has a high ION/IOFF ratio, better gate control, and higher tunnelling probability. In order to effectively reduce ambipolarity, asymmetrical doping is used at the p+ source and n+ drain, along with gate work function engineering. The stacked layers of HfO2/SiO2 gate oxide help to reduce the fringing electric field. The suggested device utilizes a dielectrically controlled technique to achieve biomolecule conjugation. This is done by etching a single nanogap cavity in the gate dielectric material towards the source end. An evaluation of the dielectric constants [K = 2.1, 2.63, 3.30, 6.3, and 12] of neutral and charged biomolecules compared to air [k = 1] is essential to determine the sensitivity of biosensors in an arid environment. The transconductance-to-current ratio (gm/Ids), switching ratio (ION/IOFF), and threshold voltage are the performance metrics used to evaluate the device sensitivity. The DM-DG–SC–InGaAs/GaAsSb HTFETpromises to be very sensitive while using less power during the detection process. It also shows that it could be a good choice for label-free biosensor applications.

Destructive dielectric breakdown of 2D muscovite mica

This study investigates the destructive breakdown (DBD) phenomenon in the van der Waals gate dielectric 2D muscovite mica (4–12 nm thick), focusing on its electrical reliability as a gate dielectric material. Capacitor test structures were electrically stressed, and the resulting impact on the physical structure was analyzed using atomic force microscopy. The volume of material removed in a DBD event is found, and the energy required (Ereq) to vaporize the volume was calculated. It is found that Ereq is proportional to the average electrical energy dissipated in the capacitor during breakdown (BD), indicating a direct correlation between damage caused during DBD and the current flow at BD location. In contrast to other thin film dielectrics, the 2D mica is highly susceptible to DBD even at very low current density (<1 A/cm2) and the abrupt, destructive BD more resembles that of thick film dielectric breakdown. An explanation for these finding is proposed in which intercalated K+ ions agglomerate around defects generated by the electrical stressing such that the defect density increases substantially in the local vicinity of BD locations, which leads to increased current and associated Joule heating after the BD event.

Retraction Note: Exploring High-Temperature Reliability of 4H-SiC MOSFETs: A Comparative Study of High-K Gate Dielectric Materials

Retraction Note: Exploring High-Temperature Reliability of 4H-SiC MOSFETs: A Comparative Study of High-K Gate Dielectric Materials

Optical properties of hafnium-dioxide derived from reflection electron energy loss spectroscopy spectra

The optical properties of HfO2 have practical applications. As an important gate dielectric material with high-k dielectric, HfO2 is beneficial to reduce the leakage current of the complementary metal-oxide-semiconductor (CMOS) gate and improves the gate structure. HfO2 also plays a key role in optical coating materials field for its high transmittance in the ultraviolet to near-infrared band, and high laser damage threshold. Therefore, it is of practical significance for the accurate knowledge of optical properties of HfO2. Here we present the optical constants and dielectric function of HfO2 based on the energy loss function (ELF) in the energy loss range of 0–200 eV for nanocrystalline film. Our new data are derived from the analysis of the reflected electron energy loss spectra by using the latest version of our reverse Monte Carlo modelling. Sum rules are used to check the reliability of the new data. We have found that up to 30 eV there are three main peaks, and the first-principles calculation also confirms the three peak structures. A comparison with previous results indicates that the ELF peak positions of HfO2 with different crystal structures are similar, but the peak intensity and shape are different. The heterogenicity of the crystal structure of HfO2 leads to different measurement results for different samples.

Controlling Fluorination Density of Soluble Polyimide Gate Dielectrics and its Influence on Organic Crystal Growth and Device Operational Stability.

Fluorinated polyimides (PIs) are among the most promising candidates for gate dielectric materials in organic electronic devices because of their solution processability and outstanding chemical, mechanical, and thermal stabilities. Additionally, fluorine (F) substitution improves the electrical properties of PI thin films, such as enhanced dielectric properties and reduced surface trap densities. However, the relationship between the fluorination density of PIs and crystal growth modes of vacuum-deposited conjugated molecules on PI thin films, which is directly related to the lateral charge transport along the PI-organic semiconductor interface, has not been systematically studied. Herein, five different soluble PIs with different F densities were synthesized, and the correlation between fluorination and thin-film properties was systematically investigated. Not only were their dielectric properties modulated, but the growth modes of the organic molecules deposited on the PI thin films also changed with increasing surface F density. This phenomenon was observed by both surface and crystallographic analyses, which resulted in extremely high operational stability of field-effect transistors and the successful fabrication of organic complementary circuits. We believe that the correlation between PI backbone fluorination and its thin-film properties will provide practical insights into the material design based on controlled molecular directed surface assembly on fluorinated polymer dielectrics.

Anisotropic dielectric dispersions and thermal behaviors in highly textured BN thin films for heat self-dissipating electronics

Mainstream high-k gate materials, such as SiO2, Al2O3, and HfZrO2, are in demand for modern electronics. However, these dielectrics possess lower thermal conductivity, significantly limiting thermal dissipation in electronic devices. Herein, we propose the utilization of complementary metal-oxide semiconductor- (CMOS) compatible high power impulse magnetron sputtering (HiPIMS) for the mass production of highly textured hexagonal boron nitride (h-BN) on (100)-, (110)-, and (111)-oriented SrTiO3 substrates. The as-prepared films exhibit distinct vertical alignments, as evidenced by HRTEM and FTIR analysis. Notably, the R value, ranging from 0.46 to 0.50, is associated with the stress in the film. Importantly, distinct anisotropies in thermal conductivity, dielectric constant, and optical band gap are observed. Furthermore, the values of thermal conductivity in these highly textured h-BN films are 4.5, 5.7, and 5.3 Wm−1K−1, which is almost three times larger than those of SiO2 (1.4 Wm−1K−1) and Al2O3 (1.35 Wm−1K−1), and even an order of magnitude larger than that of HfZrO2 (0.67 Wm−1K−1). The combination of excellent dielectric characteristics, favorable thermal conductivity, and superior stability over a broad temperature range makes this novel material outperform conventional dielectric gate materials in high-power electronics applications.

Quantum transport in WSe2/SnSe2 tunneling field effect transistors with high-k gate dielectrics

Combining two-dimensional materials and high-k gate dielectrics offers a promising way to enhance the device performance of tunneling field-effect transistor (TFET). In this work, the device performance of WSe2/SnSe2 TFET with various gate dielectric materials is investigated based on quantum transport simulation. Results show that TFETs with high-k gate dielectric materials exhibit improved on-off ratio and enhanced transconductance. The optimized WSe2/SnSe2 TFET with TiO2 gate dielectrics achieves an on-state current of 1560 μA/μm and a subthreshold swing (SS) of 48 mV/dec. The utilization of high-k gate dielectric materials results in shorter tunneling length, higher transmission efficiency, and increased electron tunneling probability. The performance of the WSe2/SnSe2 TFET would be affected by the presence of the underlap region. Moreover, WSe2/SnSe2 TFETs with La2O3 dielectric can be scaled down to 3 nm while meeting high-performance (HP) device requirements according to the International Technology Roadmap for Semiconductors (ITRS). This research presents a practical solution for designing advanced logic devices in the sub-5 nm technology node.

Analysis of electrical and hysteresis characteristics of flexible OTFT using solution-processable DPP-DTT polymer and Parylene-C

Organic thin-film transistors (OTFTs) fabricated on Parylene-C substrates have the advantages of a simple process, low cost, and flexible characteristics. This study introduces the manufacturing method and electrical characteristics of an OTFT using organic materials as the substrate, gate dielectric, and channel material. PDPP2T-TT-OD(DPP-DTT) is used as the channel material, which is a highly mobile p-type polymer with good air stability. The proposed OTFT device has flexible characteristics because it is fabricated on a Parylene-C substrate and can be used even in a curved state. Furthermore, the manufacturing process was largely achieved via a simple, low-cost solution process using spin-coating and photolithography with a photo-curable material. Under flat conditions, the threshold voltage (VTH) is approximately –3 V, the average ION/IOFF ratio is approximately 105, and the mobility is 0.84 cm2/Vs.

Optimization of structural parameters in Omega(Ω)-Shaped gate p-GaN MIS-HEMT for performance improvement

In this paper, optimization of a novel p-GaN MIS-HEMT is performed and investigated for improved performance. In the proposed device, we have incorporated an Omega (Ω) shaped gate that surrounds the dielectric layer placed above the p-GaN layer. The Ω-shaped gate p-GaN MIS-HEMT alleviates stress on the gate dielectric. In addition, the Ω-shaped gate ensures a more uniform distribution of stress on the gate dielectric, thereby decreasing the risk of dielectric breakdown and enhancing the overall reliability of the device. The optimization has been performed with respect to gate dielectric's thickness, length and material, to achieve the optimal device performance. The validation of simulation results involved calibrating device models using experimental data. The proposed device demonstrates superior breakdown voltage, enhanced threshold voltage, and decreased gate leakage current when compared to existing state-of-the-art devices. Additionally, a set of processing steps has been proposed for the potential fabrication of the proposed device.

Design and Analysis of Symmetrical Dual Gate Tunnel Field Effect Transistor with Gate Dielectric Materials in 10nm Technology

Design and Analysis of Symmetrical Dual Gate Tunnel Field Effect Transistor with Gate Dielectric Materials in 10nm Technology

Low-temperature crosslinked soluble polyimide as a dielectric for organic thin-film transistors: enhanced electrical stability and performance

We have prepared a low-temperature cross-linked soluble polyimide (SPI) as a dielectric material for organic thin-film transistors (OTFTs) to improve their electrical stability. Two types of SPIs (DOCDA/6FHAB and 6FDA/6FHAB) were synthesized by a one-step polymerization process using 5-(2,5-dioxytetrahydrofuryl)-3-methyl-3-cyclohexene-1,2-dicarboxylic anhydride (DOCDA) and hexafluoroisopropylidene diphthalic anhydride (6FDA) as the dianhydrides and 2,2-bis(3-amino-4-hydroxyphenyl)hexafluoropropane (6FHAB) as a diamine. To further enhance the electrical performance, the SPI thin films were crosslinked with methylated/ethylated (hydroxymethyl)benzoguanamine (HMBG) through a low temperature process at 160 °C. Crosslinking considerably improved the insulating properties, resulting in a substantial reduction in leakage current from 10−7 A cm−2 to 10−9 A cm−2 at 2.0 MV cm−1. When crosslinked SPIs were used as gate dielectrics in OTFTs, device stability and reliability, as measured by the off-current, threshold voltage, and hysteresis, improved significantly. Our results demonstrate the potential of crosslinked SPIs as effective gate dielectric materials for advanced organic thin-film transistors.

(Invited) Growth of Hexagonal Boron Nitride by MOCVD for Electronic and Photonic Applications

Hexagonal boron nitride (h-BN) is a 2-dimensional (2D) layered insulating material. Thanks to its wide bandgap of ~6 eV and high thermal conductivity, h-BN has been widely utilized as an ideal substrate, gate dielectric material, passivation layer, and atomic tunnelling layer for 2D electronic devices. Recently, it has gained more attention as active material for photonics applications due to its potential for stable quantum emitters in the visible spectral range, as well as deep-ultraviolet emitters and detectors due to its exceptionally high internal quantum efficiency despite its indirect bandgap. However, mechanically exfoliated bulk h-BN and h-BN films grown on catalytic metal substrates by conventional chemical vapor deposition (CVD) systems have been mainly used to study the fundamental properties, lacking in scalability for practical implementation of h-BN.Here, we exploit the scalable approach to grow h-BN on various substrates such as sapphire, Si, and GaN, by using metal-organic chemical vapor deposition (MOCVD). A few-layer h-BN films were successfully grown on those substrates. In particular, we successfully accomplished the conformal growth of few-layer h-BN over an array of Si-based nanotrenches with 45 nm pitch and the aspect ratio of ~ 7:1. Moreover, it was found that at a specific MOCVD growth condition, a very unique h-BN film can be grown on GaN substrates, in which few-layer h-BN film is suspended on GaN nanoneedles. The combination of state-of-the-art microscopic and spectroscopic analyses revealed that the suspended h-BN films exhibit unprecedented deep ultraviolet photoluminescence spectra with local variation in band-edge emission. In addition, the h-BN films show unprecedented atomic stacking configuration, the mechanism of which will be discussed with optical and structural characterizations and theoretical calculations.

RETRACTED ARTICLE: Exploring High-Temperature Reliability of 4H-SiC MOSFETs: A Comparative Study of High-K Gate Dielectric Materials

RETRACTED ARTICLE: Exploring High-Temperature Reliability of 4H-SiC MOSFETs: A Comparative Study of High-K Gate Dielectric Materials

Impact of Parametric Variation on the Characteristics and Performance of CNTFET Inverter

In this paper, a simple carbon nanotube field effect transistor (CNTFET)-based inverter has been simulated and the impacts of changing various design and process parameters on its characteristics and performance have been analysed using HSPICE. The 32 nm CNTFET model of Stanford University has been used here for the simulation of the inverter. The simulation results and the voltage transfer characteristics (VTC) curve of the inverter have been extracted for (i) different channel lengths, (ii) top gate di-electric material thickness (tox), (iii) pitch value (iv) the number of tubes in CNTFET channel region and (v) chirality of the CNT. It has been observed that the VTC curve changes significantly with different values of these parameters. Some important output parameters like maximum dc current, power, rise time, fall time, average propagation delay, etc. have been measured in each case. Changes in maximum power consumption value due to the change in different parameter values are observed through plotted graphs. Output dc current vs. input voltage graphs have been plotted for different chirality of the tubes, the number of the tubes, and pitch values between n-type CNTFET and p-type CNTFET of the inverter.

Dual‐logic‐in‐memory implementation with orthogonal polarization of van der Waals ferroelectric heterostructure

AbstractThe rapid advancement of AI‐enabled applications has resulted in an increasing need for energy‐efficient computing hardware. Logic‐in‐memory is a promising approach for processing the data stored in memory, wherein fast and efficient computations are possible owing to the parallel execution of reconfigurable logic operations. In this study, a dual‐logic‐in‐memory device, which can simultaneously perform two logic operations in four states, is demonstrated using van der Waals ferroelectric field‐effect transistors (vdW FeFETs). The proposed dual‐logic‐in‐memory device, which also acts as a two‐bit storage device, is a single bidirectional polarization‐integrated ferroelectric field‐effect transistor (BPI‐FeFET). It is fabricated by integrating an in‐plane vdW ferroelectric semiconductor SnS and an out‐of‐plane vdW ferroelectric gate dielectric material—CuInP2S6. Four reliable resistance states with excellent endurance and retention characteristics were achieved. The two‐bit storage mechanism in a BPI‐FeFET was analyzed from two perspectives: carrier density and carrier injection controls, which originated from the out‐of‐plane polarization of the gate dielectric and in‐plane polarization of the semiconductor, respectively. Unlike conventional multilevel FeFETs, the proposed BPI‐FeFET does not require additional pre‐examination or erasing steps to switch from/to an intermediate polarization, enabling direct switching between the four memory states. To utilize the fabricated BPI‐FeFET as a dual‐logic‐in‐memory device, two logical operations were selected (XOR and AND), and their parallel execution was demonstrated. Different types of logic operations could be implemented by selecting different initial states, demonstrating various types of functions required for numerous neural network operations. The flexibility and efficiency of the proposed dual‐logic‐in‐memory device appear promising in the realization of next‐generation low‐power computing systems.image

Wafer-scale MOCVD grown WS2 with normally off transistor behavior and its general application on different amorphous substrates

In this study, we investigated various approaches to manipulate the flake density, size, and thickness of two-dimensional transition metal dichalcogenides by independently tuning the precursors and process conditions of the metal–organic chemical vapor deposition system. Normally off device characteristics were realized for both the as-grown and transferred cases. Furthermore, we demonstrated the versatility of our growth method by applying it to several commonly used gate dielectric materials, such as SiO2, SiNx, and AlOx.

High photoresponsivity MoS2 phototransistor through enhanced hole trapping HfO2 gate dielectric

Phototransistor using 2D semiconductor as the channel material has shown promising potential for high sensitivity photo detection. The high photoresponsivity is often attributed to the photogating effect, where photo excited holes are trapped at the gate dielectric interface that provides additional gate electric field to enhance channel charge carrier density. Gate dielectric material and its deposition processing conditions can have great effect on the interface states. Here, we use HfO2 gate dielectric with proper thermal annealing to demonstrate a high photoresponsivity MoS2 phototransistor. When HfO2 is annealed in H2 atmosphere, the photoresponsivity is enhanced by an order of magnitude as compared with that of a phototransistor using HfO2 without annealing or annealed in Ar atmosphere. The enhancement is attributed to the hole trapping states introduced at HfO2 interface through H2 annealing process, which greatly enhances photogating effect. The phototransistor exhibits a very large photoresponsivity of 1.1 × 107 A W−1 and photogain of 3.3 × 107 under low light illumination intensity. This study provides a processing technique to fabricate highly sensitive phototransistor for low optical power detection.

Performance improvement of junctionless SOI-MOSFETs by a superior depletion technique

This work uses a superior depletion technique to present a junctionless silicon-on-insulator (SOI) metal-oxide field-effect transistor (MOSFET) in a 14 nm regime. The suggested technique embeds a P-type area into the buried silicon oxide (SiO2) layer. The p-silicon area has several effects on the proposed structure (EPB-JLSM): First, it helps us attain a full depletion area in the channel. Second, the self-heating improves due to the higher thermal conductivity of silicon than the silicon nitride. Finally, the embedded area causes the lower hole concentration (high Vds at accumulation mode), resulting in a better kink effect. Also, we discuss the impact of inserting the P-silicon area geometry into the buried layer on the DC performance device, such as height and thickness. The P-silicon area decreases the leakage current (IOFF) by three orders of magnitude (∼1000%), and also slightly enhances the drive current (ION) (∼20%), and reduces subthreshold swing (SS) from 186 to 109 mV dec−1 (∼71%) compared to a typical junctionless SOI MOSFET (C-JLSM). Furthermore, we discuss the effect of the buried region and gate insulator materials on the proposed device’s performance.