Gate Dielectric Films Research Articles

Physical Mechanism of Threshold Voltage Modulation by Ge Channel Ion Implantation in the TiN/HfO2 Gate Stack Systems

We extensively investigated the physical origin of the threshold voltage VTH modulation by the Ge channel ion implantation (I/I) in HfO2/TiN/polycrystalline Si gate stack systems. The possible VTH modulation factors were carefully distinguished from each other by changing the channel dopant concentration and the thickness of the gate dielectric films. It was found that the changes in energy-band offset and dopant concentration in the channel region are minor factors of the VTH modulation. However, it was also found that ΔVTH is sensitive to the oxidation condition of the interfacial oxide layer; a longer oxidation induces a larger ΔVTH. From the X-ray spectroscopy, we found that a Ge pile-up at the interfacial layer/channel interface occurs, and that the VTH modulation range correlates well with the amount of piled-up Ge.

High-performance ZnO thin-film transistor fabricated by atomic layer deposition

We report the fabrication and characteristics of a ZnO thin-film transistor (TFT) using a 50 nm thick ZnO film as an active layer on an Al2O3 gate dielectric film deposited by atomic layer deposition. Lowering the deposition temperature allowed the control of the carrier concentration of the active channel layer (ZnO film) in the TFT device. The ZnO TFT fabricated at 110 °C exhibited high-performance TFT characteristics including a saturation field-effect mobility of 11.86 cm2 V−1 s−1, an on-to-off current ratio of 3.09 × 107 and a sub-threshold gate-voltage swing of 0.72 V decade−1.

Pr3Si6N11/Si3N4 Stacked High-k Gate Dielectrics with High Quality Ultrathin Si3N4 Interfacial Layers

In Order to utilize the entire capability of the silicon crystal, we must fabricate LSI on any crystal orientation silicon surface using three dimensional structure MOS transistors, i.e., very high integrity gate insulator films must be formed on any crystal orientation silicon surface with the same formation speed, i.e., the radical oxidation (SiO2) and the radical nitridation (Si3N4) at low temperatures. Accumulation mode balanced CMOS fabricated on (551) surface silicon SOI substrate has been theoretically confirmed to exhibit super high speed performance over 100 GHz clock rate at 45 nm technology node where the gate insulator film to silicon interface is atomically flat and the series resistance of the source and the drain electrode is decreased by a factor of two orders of magnitude by introducing very low contact resistance new silicide materials to n+ region (ErSi2) and p+ region (Pr2Si), respectively.

Measurement of oxygen diffusion in nanometer scale HfO2 gate dielectric films

Diffusion of oxygen ions in thin (≲40 Å) HfO2 gate dielectric films is measured using transient gate currents. The diffusion coefficient is estimated to be ∼1×10−14 cm2/s at room temperature, and is observed to be thermally activated with an activation energy of ∼0.52 eV for nanometer scale HfO2 films. The diffusion results are shown to be consistent with those for positively charged oxygen vacancies in bulk samples of similar oxides, and first principle calculation results for oxygen vacancy diffusion in thin HfO2 films. Thus, we demonstrate a method for measuring oxygen diffusion in thin HfO2 films where diffusion measurements by the conventional techniques have been elusive.

A Distributed Model for Border Traps in $\hbox{Al}_{2} \hbox{O}_{3}-\hbox{InGaAs}$ MOS Devices

A distributed border trap model based on tunneling between the semiconductor surface and trap states in the gate dielectric film is formulated to account for the observed frequency dispersion in the capacitance and conductance of Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /InGaAs MOS devices biased in accumulation. The distributed circuit model is more physical and descriptive than previous lumped circuit border trap models in the literature. The distributed model correctly depicts the frequency dependence of both capacitance and conductance data in accumulation. A border trap volume density is extracted from the quantitative agreement with measured data.

Influences of surface reconstruction on the atomic-layer-deposited HfO2/Al2O3/n-InAs metal-oxide-semiconductor capacitors

We report the characteristics of HfO2/Al2O3/n-InAs metal-oxide-semiconductor capacitors on different reconstructed surface InAs substrates. The HfO2/Al2O3 gate dielectric films deposited on InAs were used to study the interfacial reaction. Compared with (2×4)-surface sample, improvements of capacitance-voltage characteristics for (1×1)-surface sample with lower frequency-dependent capacitance dispersion and higher inversion capacitance are attributed to lower indium composition and less arsenic oxide at Al2O3/InAs interface, as confirmed by x-ray photoelectron spectroscopy. It indicates that the equivalent dangling bond of cations and anions on (1×1)-surface sample tends to avoid the oxidization process and become less pinning.

Using Chemical-Mechanical Polishing for Planarizing a High-&lt;I&gt;κ&lt;/I&gt; Nanocomposite Polyimide Insulator for Organic Thin Film Transistors Application

To solve the large leakage current of the heavily blended nanocomposite (Polyimide and nano-TiO2 particles) gate dielectric film exhibiting a high-kappa, the chemical-mechanical polishing (CMP) was adopted to flatten the surface of the PI-TiO2 nanocomposite film. An extremely high dielectric constant (is congruent to 13) of the nanocomposite with CMP treatment is obtained and its leakage current is comparable to that of the neat polyimide in our studies. An OTFT based on the nanocomposite gate dielectric exhibiting high capacitance and a smooth surface after CMP treatment shows very promising performance. Compared with the OTFT based on the neat polyimide gate dielectric, the threshold voltage is improved from -22 to -5 (V), the sub-threshold voltage is decreased from 3.44 to 0.50 (V/dec), the current on/off ratio is increased from 1.6 x 10(6) to 3.53 x 10(8), and the mobility is increased from 0.416 to 0.624 (cm2V(-1)s(-1)). Moreover, it is worth noting that the hysteresis effect of OTFT based the nanocomposite can be significantly reduced due to the few charge trapped in the interface when the nanocomposite dielectric surface was further polished by CMP treatment.

Effect of Rapid Thermal Annealing on Structural and Electrical Characteristics of Ni-Al-O Gate Dielectrics

The high-k Ni-Al-O gate dielectric films were deposited on Si(100) and platinized Si(111) substrates by reactive pulsed-laser deposition(PLD) at 400℃,and then annealed in a rapid thermal annealing furnace at various temperatures ranging from 600℃ to 750℃.The structural and electrical properties of the Ni-Al-O films were investigated.It is found that Ni-Al-O thin film annealed up to 750℃ is amorphous and the root-mean-square roughness of the film is less than 0.5 nm.The dielectric constant of the film measured at the frequency of 1 MHz is determined to be 9.9 with Pt/Ni-Al-O/Pt structure.The capacitance and leakage current density of the film annealed above 700℃ are 135 pF and 7.0×10 7 A/cm2,respectively.The results indicate that the amorphous Ni-Al-O film is a promising candidate for high-k gate dielectric.

Fabrication of High-k Gate Insulator Films by Atomic Layer Deposition and Their Properties Influenced by Substrate Hydrophilicity

We examined the impact of surface chemical nature prior to atomic layer deposition (ALD) to the electrical properties of high-k gate stacks on Si substrates. We confirmed that poor electrical film quality in ALD-HfO2 fabricated on H-terminated surfaces is drastically improved by changing the surface species terminating topmost Si bonds to be hydrophilicized. Especially, the high-k gate stacks fabricated on the surfaces chemically controlled by “oxygen-termination” technique showed excellent interfacial electrical quality without creating thick interfacial SiO2 layer.

Effect of chemical surface treatments on interfacial and electrical characteristics of atomic-layer-deposited Al2O3 films on Ge substrates

The Ge surfaces were cleaned and passivated by two kinds of chemical pretreatments: conventional combination of HF+(NH4)2S, and new one of HBr+(NH4)2S. The chemical states and stability at passivated Ge surfaces were carefully characterized. The influence of chemical surface treatments on the interface and electrical properties of Al2O3 gate dielectric films on Ge grown by atomic layer deposition (ALD) has been investigated deeply. It is found that the combination of HBr and (NH4)2S can remove more Ge–O bonds on the Ge surface compared to that of conventional HF and (NH4)2S with excellent stability. X-ray photoelectron spectroscopy (XPS) reveals that HBr and (NH4)2S treated Ge surface has a mixture states of GeOx (9.25%) and GeS (7.40%) while HF and (NH4)2S treated Ge surface has a mixture states of GeOx (16.45%) and GeS (3.37%). And the Ge–S peak from the surface of Ge substrates decreases a little after the HBr and (NH4)2S treated Ge surface was exposed in the ambient for 300min, which suggests the Ge surface is stable to oxidants. The Al2O3 films on HBr and (NH4)2S treated Ge substrates exhibits better electrical properties such as large capacitance, decreased leakage current density by ∼two orders of magnitude, and less C–V hysteresis. This indicates that a reduction in charge traps possibly at the interface and more interface traps are terminated by sulfur. The surface treatment of HBr and (NH4)2S seems to be very promising in improving the quality of high-k gate stack on Ge substrates.

Dependence of the Decomposition of Trimethylaluminum on Oxygen Concentration

Trimethylaluminum (TMA) is often used as a source gas for composite semiconductor or gate insulator films containing aluminum. However, TMA readily reacts with and this reaction causes film performance to degrade. Film formation is affected by the decomposition properties of the source gas, so it is important to investigate the influence of on the decomposition behavior of TMA. The starting decomposition temperature of TMA was in an tube filled with Ar gas, and the decomposition rate increased rapidly above . However, when TMA was heated in an atmosphere containing more than , the temperature at which TMA began to decompose increased. It is assumed that this phenomenon resulted from the formation of methoxy groups through reaction between TMA and . Thus, the presence of in TMA not only caused the films to be contaminated with oxygen atoms but also altered the decomposition behavior of TMA. This means that fluctuations in the deposition rate and film performance are caused by the presence of in TMA when deposition conditions are otherwise kept constant. As a result, it is desirable that the concentration present in TMA is maintained below during deposition.

Stress-Induced Deterioration of Nanocrystalline ITO Embedded ZrHfO High-k Nonvolatile Memories

The stress-induced deterioration phenomenon of the nc-ITO embedded Zr-doped HfO2 high-k gate dielectric film has been studied. The deterioration process is detectable from the decrease of the capacitance in the accumulation region and the shift of flatband voltage as well as the change of the amount of induced charges. In addition, the relaxation current and Coulomb blockage effect are influenced by the stress-induced process. Moreover, the nc-ITO embedded high-k capacitor shows the trap-assisted tunneling phenomenon and the Poole-Frenkel emission mechanism.

Effect of nitrogen doping on the properties of AlSiO film for wide bandgap semiconductors

A gate insulator film with a wide bandgap and a high dielectric constant is required to achieve high-power field effect transistors (FET) using wide bandgap semiconductors such as SiC, GaN, and diamond. It is observed that an aluminum silicon oxide (AlSiO) film containing 11% nitrogen has a high resistivity of 5 × 10 15 Ω cm, and the leakage current of a nitrogen-doped aluminum silicon oxide (AlSiON) film is also suppressed at high temperature, as compared to the AlSiO film. For example, the leakage current at 240 °C is four orders of magnitude smaller than that of the AlSiO film, suggesting that the AlSiON film is applicable to high temperature operation of wide bandgap semiconductor devices.

Effect of Ti incorporation on the interfacial and optical properties of HfTiO thin films

Interfacial and optical properties of HfTiO films with different Ti concentration grown by radio frequency reactive magnetron sputtering have been investigated by x-ray photoelectron spectroscopy (XPS) and spectroscopy ellipsometry (SE). XPS spectra indicate that interfacial layer is formed unavoidably for Ti doped and undoped HfO2 thin films and the interfacial structure is stable for Ti doped films. The composition of interfacial layer is most likely silicate and SiOx. Meanwhile, SE results indicate that the band gap of HfTiO thin films decreases with the increase in Ti concentration. Further results show that the valence band offset (ΔEv) decreases from 2.32 to 1.91 eV while the conduction band offset (ΔEc) decreases from 2.05 eV to 0.99 with the increase in Ti content. The optical constants consist of refractive index and extinction coefficient have also been investigated to provide the valuable references to prepare and select the HfTiO thin films for future high-k gate dielectrics.

The role of nano particles (Si) in gate dielectric

The progressively decreasing feature size of the circuit components, particles and electronic devices has tremendously increased the need for studying and investigating the nano structural properties of materials. We have grown titanium oxide on the Si (100) substrate at 500°C and one atmosphere pressure. Some researchers have believed that an intermediate silicon oxide film can be made between titanium oxide film and substrate but which turned to be of less use. We added silicon nano particles (100 nm) into titanium oxide film that could modify the titanium oxide morphology as revealed in x-ray diffraction patterns and scanning electron microscopy images. The obtained results show that the existence of silicon nano particles in titanium oxide film resulted in better stability. The improved film can thus be used as a good gate dielectric film for the future CMOS (Complementary metal oxide semiconductor) devices.

Fabrication of self-aligned TFTs with a ultra-low temperature polycrystalline silicon process on metal foils

We have fabricated self-aligned thin-film transistors (TFTs) using a ultra-low temperature ( T < 200 °C) polycrystalline silicon process on stainless steel foil substrates. The overall processing scheme and technical details were discussed from the viewpoint of electrical and mechanical stabilities. Large grain poly-Si films were obtained with sequential lateral solidification (SLS) method. Plasma enhanced atomic layer deposition (PEALD) method was used to form Al 2O 3 gate dielectric films. The TFT performances were enhanced by plasma oxidation of the polycrystalline Si surface prior to Al 2O 3 gate dielectric film deposition. The fabricated TFT showed a field effect mobility of 95 cm 2/Vs, a threshold voltage of −3 V and a sub-threshold swing of 0.45 V/dec.

Study of negative oxygen vacancies in Gd2O3-doped HfO2 thin films as high-k gate dielectrics

Negative oxygen vacancies are the origin of intrinsic shallow electron traps in HfO2 gate dielectrics which degrade the electrical properties of the field-effect transistors. In this paper, we study the effect of Gd2O3 doping on the reduction of negative oxygen vacancies in HfO2 thin films. After the deposition of both pure and doped gate dielectric thin films, electrical characterizations such as capacitance–voltage (C–V) and current–voltage (I–V) have been carried out. C–V measurement reveals the presence of negative oxygen vacancies in pure HfO2 dielectrics and a reduction of negative oxygen vacancies after the incorporation of Gd2O3. I–V measurements show a pronounced reduction of leakage current for the doped thin films which attributes to less negative oxygen vacancies. Gd2O3 doping of 15.6 at% has the least negative oxygen vacancies and best dielectric performance. X-ray photoelectron spectroscopy measurements indicate that Gd2O3 has been incorporated into HfO2 and the negative oxygen vacancies are partly eliminated.

The influence of lanthanum doping position in ultra-thin HfO 2 films for high-k gate dielectrics

Lanthanum dopant positioning at HfO 2 ultra-thin films was achieved by the co-sputtering method. The physical properties of graded doping HfO 2/HfLaO/p-Si and HfLaO/HfO 2/p-Si structures after 850 °C postannealing were compared. The thickness of the monolayer was analyzed by X-ray reflectivity and confirmed by the multiple beam interference model. The HfO 2 and silicate phases were characterized by X-ray diffraction patterns. It is found that crystallization depends on the ratio of stacked film thicknesses, and the HfLaO/HfO 2/Si structure has more silicate formation at the interface than the HfO 2/HfLaO/Si structure. Metal–insulator–semiconductor capacitors were fabricated. The electrical properties including leakage current, conduction mechanism, flatband voltage shift, and barrier height were studied.

High Performance of Ultralow Temperature Polycrystalline Silicon Thin Film Transistor on Flexible Metal Foil Substrate

A high performance ultralow temperature polycrystalline silicon (poly-Si) thin film transistor (TFT) was obtained on a flexible metal foil substrate using the optimization of a benzocyclobutene (BCB) planarization process for a rough flexible metal foil substrate surfaces, the high quality SiO2 interface layer formation between the gate dielectric film and the poly-Si film using plasma oxidation, and a successful crystallization of large grain poly-Si films with a sequential lateral solidification (SLS) method. High performances with field effect mobilities of 196 and 95 cm2 V-1 s-1, threshold voltages of 1.6 and -1.5 V and sub-threshold swings of 0.53 and 0.45 V/decade were obtained for n-channel metal–oxide–semiconductor (nMOS) and p-channel metal–oxide–semiconductor (pMOS) TFT on flexible metal foil substrate, respectively.

Hole-Trapping Mechanism and SILC of Dual-Layer nc-ITO Embedded ZrHfO High-k Nonvolatile Memories

MOS capacitors containing singe- and dual-layer nc-ITO embedded ZrHfO high-k gate dielectric films were fabricated and characterized for nonvolatile memory functions and reliability. The addition of the second nc-ITO into the high-k dielectric enhanced the memory function of the devices, e.g., a larger memory window, more sensitive to the gate bias voltage, and longer charge retention time. From the SILC test, the dual-layer nc-ITO sample also showed more pronounced Coulomb blockade phenomena than the single nc-ITO embedded sample, which is consistent with the hole-trapping characteristics. The novel charge storage characteristics of the dual-layer nc-ITO embedded high-k make it suitable for future memory applications.