Pr3Si6N11/Si3N4 Stacked High-k Gate Dielectrics with High Quality Ultrathin Si3N4 Interfacial Layers

Abstract

In Order to utilize the entire capability of the silicon crystal, we must fabricate LSI on any crystal orientation silicon surface using three dimensional structure MOS transistors, i.e., very high integrity gate insulator films must be formed on any crystal orientation silicon surface with the same formation speed, i.e., the radical oxidation (SiO2) and the radical nitridation (Si3N4) at low temperatures. Accumulation mode balanced CMOS fabricated on (551) surface silicon SOI substrate has been theoretically confirmed to exhibit super high speed performance over 100 GHz clock rate at 45 nm technology node where the gate insulator film to silicon interface is atomically flat and the series resistance of the source and the drain electrode is decreased by a factor of two orders of magnitude by introducing very low contact resistance new silicide materials to n+ region (ErSi2) and p+ region (Pr2Si), respectively.