Gate Dielectric Films Research Articles

Property of an AlGaN/GaN MIS Diode with Si<sub>3</sub>N<sub>4</sub>/Al<sub>2</sub>O<sub>3</sub> Bilayer Gate Dielectric Films

Metal-insulator-semiconductor (MIS) diodes with Si3N4/Al2O3 bilayer gate dielectric films deposited on an AlGaN/GaN heterostructure were fabricated, where the Si3N4 layer played a role of etching stopped layer to protect the Al2O3 film from being damaged. Compared with traditional Schottky diodes, a distinct suppression of gate leakage current was achieved for the MIS diodes both at forward and reverse bias, and the dominant leakage current mechanism is Fowler–Nordheim tunneling. The 2DEG density extracted from C-V curves was 3~7 ́1013cm-2, in the same order of magnitude as Schottky diodes and hall measurement. Although the existence of the bilayer dielectric did not affect the 2DEG density at the interface of AlGaN/GaN, Si3N4 layer shared more gate bias and led to more gate bias required to deplete 2DEG and turn down the devices, moreover, Si3N4 layer had no effect on suppressing the forward or reverse gate leakage current due to its narrow band gap width and band bending compared with a single Al2O3 film. The experimental results provided a reference for the design of gate dielectric film structure for AlGaN/GaN high-electron-mobility transistors (HEMTs).

Thermal annealing, interface reaction, and lanthanum-based sub-nanometer EOT gate dielectrics

In future nanoscale complementary metal-oxide-semiconductor (CMOS) devices, the high dielectric constant (high-k) gate dielectric film will be shrunk down to a couple of nanometers or down to the sub-nanometer range in the sense of oxide equivalent thickness (EOT). However, as high-k materials, including La2O3 which has been considered to be one of the promising next generation gate dielectric materials, are only marginally stable on the silicon substrate, some nominal temperature processes used for the device fabrication may still give rise to interface reactions and result in a low-k interface layer which will be a critical constraint for achieving the ultrathin EOT gate dielectric film. In this work, some issues related to the material interaction at the lanthanum oxide/Si and lanthanum oxide/metal interfaces will be discussed with the supports of interface bonding structures as revealed by using angle-resolved x-ray photoelectron spectroscopy (ARXPS) measurements. We show that thermal annealing at temperature above 500 °C would result in the migration of Si atoms deep into the bulk of the La2O3 film and formation of silicate phases both at the interface and in the bulk. These effects would significantly lower the dielectric constant and thus increases the effective thickness of the dielectric film from the equivalent silicon oxide thickness (EOT) point of view.

Dielectric thin films for GaN-based high-electron-mobility transistors

The effects of dielectric thin films on the performance of GaN-based high-electron-mobility transistors (HEMTs) were reviewed in this work. Firstly, the nonpolar dielectric thin films which act as both the surface passivation layers and the gate insulators of the high-frequency GaN-based high-electron-mobility transistors were presented. Furthermore, the influences of dielectric thin films on the electrical properties of two-dimensional electron gas (2DEG) in the AlGaN/GaN hetero-structures were analyzed. It was found that the additional in-plane biaxial tensile stress was another important factor besides the change in surface potential profile for the device performance improvement of the AlGaN/GaN HEMTs with dielectric thin films as both passivation layers and gate dielectrics. Then, two kinds of polar gate dielectric thin films, the ferroelectric LiNbO3 and the fluorinated Al2O3, were compared for the enhancement-mode GaN-based HEMTs, and an innovative process was proposed. At last, high-permittivity dielectric thin films were adopted as passivation layers to modulate the electric field and accordingly increase the breakdown voltage of GaN-based HEMTs. Moreover, the polyimide embedded with Cr particles effectively increased the breakdown voltage of GaN-based HEMTs. Finally, the effects of high-permittivity dielectric thin films on the potential distribution in the drift region were simulated, which showed an expanded electric field peak at the drain-side edge of gate electrode.

The impact of atomic layer deposited SiO2passivation for high-k Ta1−xZrxO on the InP substrate

Metal–oxide-semiconductor (MOS) capacitors with an amorphous Ta1−xZrxO composite gate dielectric film and a SiO2passivation layer were fabricated on an indium phosphide (InP) substrate.

Design and fabrication of field-effect biosensors for biochemical detection.

Biochemically sensitive field-effect sensors are fabricated with simplified chip technology. Its fabrication process flow is designed based on metal gate complementary metal-oxide semiconductor technology, in which only six pattern masks are employed. The sensors are measured as field modulation resistors since they are made in its depletion mode. The milliampere magnitude response of conducting currents from certain biochemical materials achieves distinct sensitivity when measured on our fabricated sensors with different sensitive areas of W/L = 4.2 and 20.0. To check the stability of the sensor, up to 20 repeated tests are conducted on the same sensor chip operated in its three states, in which no materials (blank state, called 'blank'), pure water and biochemical materials are coated on its gate dielectric film, respectively. Measured results show that the response currents for certain materials are distributed in certain current range. Taking the response current of blank as a reference value, the response current of pure water is positive but very close to that of blank because of the small electric dipole properties of pure water. However, the response current of biochemical materials are negative and far apart from that of blank, because the biochemical materials have large electric dipole properties and clearly show measurement resolution.

Modification of a polymer gate insulator by zirconium oxide doping for low temperature, high performance indium zinc oxide transistors

Indium zinc oxide (IZO) thin film transistors (TFTs) with poly(4-vinylphenol-co-methylmethacrylate) (PVP-co-PMMA) gate insulators were fabricated at a low temperature (250 °C). The bottom gate IZO TFTs with a PVP-co-PMMA gate electric film exhibited inferior device performance to the top gate IZO TFTs, which was attributed to sputtering damage of the underlying polymer gate dielectric film during IZO channel formation. The charge carrier transport and interface properties of the IZO TFTs could be further improved by introducing a ZrO2 precursor to the polymer gate insulator. The ZrO2 molecules were well dispersed in the polymer film. The resulting hybrid dielectric film showed a higher capacitance and a smoother morphology than the PVP-co-PMMA dielectric film. The hybrid dielectric-gated IZO TFT had a high mobility of 28.4 cm2 V−1 s−1, low subthreshold gate swing of 0.70 V per decade, and a high Ion/off ratio of 4.0 × 107.

Interface characterization of nitrogen plasma‐treated gate oxide film formed by RTP technology

We described thin nitrogen plasma‐treated gate oxide film formed by rapid thermal process technology. This thin nitrogen plasma‐treated gate oxide film has been formed using remote plasma nitridation process onto in situ steam generated oxide layer. We investigated the nitrogen profile within the gate dielectric film formed by this technique using SIMS analysis. The result shows that nitrogen concentration profile is composed of high at top surface and low at SiO2/Si interface. The peak concentration of nitrogen is placed at near top place and goes rapidly down to SiO2/Si interface. This nitrogen profile results in excellent boron diffusion barrier characteristics and superior interface properties for p+PMOSFET. We also performed the electrical analysis such as capacitance–voltage (C–V), gate leakage current, dielectric breakdown voltage and time‐to‐breakdown (TBD) measurement. It has been found that this thin nitrogen plasma‐treated gate oxide film results in superior electrical reliability having significant lower leakage current, superior dielectric strength and outstanding TBD. Copyright © 2014 John Wiley & Sons, Ltd.

12.5 A/350 V AlGaN/GaN‐on‐Si MOS‐HEMT with low specific on‐resistance and minimal threshold hysteresis

An AlGaN/GaN metal-oxide semiconductor (MOS) high-electron mobility transistor (HEMT) on silicon substrate was obtained with 8 nm Al2O3 gate dielectric films grown using atomic layer deposition. The MOS-HEMT shows a low specific on-resistance of 0.57 Omega.mm(2), a large maximum saturate drain current of 12.5 A and a minimal threshold hysteresis of 0.05 V. Low specific on-resistance, large maximum saturate drain current and minimal threshold hysteresis show that the fabricated MOS-HEMT is very suitable for power switching applications.

Materials and interfaces issues in pentacene/PTCDI-C8 ambipolar organic field-effect transistors with solution-based gelatin dielectric

Gelatin is a natural protein, which works well as the gate dielectric for pentacene/N,N-dioctyl-3,4,9,10-perylene tetracarboxylic diimide (PTCDI-C8) ambipolar organic field-effect transistors (OFETs) in air ambient and in vacuum. An aqueous solution process was used to form the gelatin gate dielectric film on poly(ethylene terephthalate) (PET) by spin-coating and subsequent casting. Pentacene morphology and interface roughness are two major factors affecting the electron and hole field-effect mobility (μFE) values of pentacene/PTCDI-C8 ambipolar OFETs in vacuum and in air ambient. In contrast, water absorption in gelatin has higher contribution to the electron and hole μFE values in air ambient. The ambipolar performance of pentacene/PTCDI-C8 ambipolar OFETs depends on their layer sequence. For example, when PTCDI-C8 is deposited onto pentacene, i.e. in the structure of PTCDI-C8/pentacene, unbalanced ambipolar characteristics appear. In contrast, better ambipolar performance occurs in the structure of pentacene/PTCDI-C8. The optimum ambipolar characteristics with electron μFE of 0.85cm2V−1s−1 and hole μFE of 0.95cm2V−1s−1 occurs at the condition of pentacene (40nm)/PTCDI-C8 (40nm). Surprisingly, water absorption plays a crucial role in ambipolar performance. The device performance changes tremendously in pentacene/PTCDI-C8 ambipolar OFETs due to the removal of water out of gelatin in vacuum. The optimum ambipolar characteristics with electron μFE of 0.008cm2V−1s−1 and hole μFE of 0.007cm2V−1s−1 occurs at the condition of pentacene (65nm)/PTCDI-C8 (40nm). The roles of layer sequence, relative layer thickness, and water absorption are proposed to explain the ambipolar performance.

Annealing temperature dependence on the structural and optical properties of sputtering-grown high-k HfO2 gate dielectrics

High-k gate dielectric HfO2 thin films have been deposited on Si and quartz substrates by radio frequency magnetron sputtering. The structural characteristics, surface morphology, and optical properties of the HfO2/Si gate stacks at various post-annealing temperatures were examined by X-ray diffraction (XRD), atomic force microscopy (AFM), fourier transform infrared spectroscopy (FTIR), ultraviolet–visible spectroscopy (UV–Vis spectroscopy), and spectroscopic ellipsometry (SE). XRD measurement indicates that the 80 W-deposited HfO2 films demonstrate a polycrystalline structure. AFM measurements illustrate that the root mean square of the HfO2 thin films demonstrates an apparent increase with increasing the annealing temperature. Analysis from FTIR indicates that the Si–O–Si bonds vibration peak position shift toward lower wave numbers with increasing the annealing temperature. Combined with UV–Vis spectroscopy and SE measurements, it can be noted reduction in band gap with an increase in annealing temperature has been confirmed. Additionally, increase in refractive index (n) has been confirmed by SE.

Interaction of Gd and N incorporation on the band structure and oxygen vacancies of HfO2 gate dielectric films

The interaction of Gd and N incorporation on the band gap, band offset, and oxygen vacancies of HfO2 high-k gate dielectric films has been investigated. The results show that introducing N (9.7% and 17.4%) and Gd into HfO2 does not dramatically reduce the band gap due to the counteracting effect of Gd doping. Most importantly, Gd and N co-doping increases the conduction band offset of HfO2 and leads to a much better band offset symmetry compared to undoped or Gd-monodoped HfO2. Compared with Gd, N plays a more significant role in improving the band-offset symmetry. The oxygen vacancies are greatly suppressed by Gd and N co-doping under the suitable doping amounts.

Modulation of the structural and optical properties of sputtering-derived HfO2 films by deposition power

High-k gate dielectric HfO2 thin films have been deposited on Si and quartz substrate by radio frequency magnetron sputtering. The structural and optical properties of HfO2 thin films related to deposition power are investigated by X-ray diffraction (XRD), fourier transform infrared spectroscopy (FTIR), atomic force microscopy (AFM), ultraviolet–visible spectroscopy (UV–Vis), and spectroscopic ellipsometry (SE). Results confirmed by XRD have shown that the as-deposited HfO2 thin films are not amorphous state but in monoclinic phase, regardless of deposition power. Analysis from FTIR indicates that an interfacial layer has been formed between the Si substrate and the HfO2 thin film during deposition. AFM measurements illustrate that the root mean square (RMS) of the as-deposited HfO2 thin films’ surface demonstrates an apparent reduction with the increase of deposition. Combined with UV–Vis and SE measurements, it can be noted reduction in band gap with an increase in power has been observed. Additionally, increase in refractive index (n) has been confirmed by SE.

Microstructure optimization and optical and interfacial properties modulation of sputtering-derived HfO2 thin films by TiO2 incorporation

TiO2-doped HfO2 gate dielectric thin films have been deposited on Si(100) substrates by RF sputtering. The component, morphology, structure, optical and interfacial properties of Hf1−xTixO2 films related to TiO2 concentration are systematically investigated by atomic force microscope (AFM), X-ray diffraction (XRD), spectroscopic ellipsometry (SE), X-ray photoelectron spectroscopy (XPS), and Fourier transformation infrared (FTIR). By employing Cauchy–Urbach model, the optical constants, such as refractive index (n), extinction coefficient (k), absorption coefficient (α), and optical band gap (Eg) have been determined precisely. Measurements from XRD have confirmed that TiO2 incorporating into HfO2 films leads to the increase of the crystallization temperature of HfO2 films with increasing the TiO2 concentration. SE analyses have indicated that reduction in band gap and refractive index has been observed with increasing the TiO2 component in Hf1−xTixO2 films. The increase in Urbach parameter EU with the increase of TiO2 concentration also suggests the rise in disorder for Hf1−xTixO2 films. FTIR measurements for Hf1−xTixO2/Si gate stack indicate the existence of the interfacial layer regardless of the TiO2 concentration. For the 9% TiO2-doped HfO2 samples, the shift in FTIR characteristic peak suggests the formation of the silicate layer, which leads to the suppressed interfacial layer growth during deposition. As a result, it can be conclude that the TiO2 component in Hf1−xTixO2 films should be controlled precisely to guarantee interfacial properties of Hf1−xTixO2/Si gate stacks.

The effect of gate dielectric modification and film deposition temperature on the field effect mobility of copper (II) phthalocyanine thin-film transistors

The change of the field effect mobility of copper (II) phthalocyanine (CuPc) ultra-thin films with the change of dielectric surface and deposition temperature has been systematically investigated. CuPc films are prepared on bare and modified SiO2 substrates at different deposition temperatures. The crystalline structure and morphology of the films have been characterized by x-ray diffraction and atomic force microscopy. The observed device parameters show that the dielectric surface modification reduces the off-state mobile charge carrier density and interfacial trap density. Dielectric surfaces with lower or comparable surface energy to that of CuPc are found to produce devices with higher mobility. The dependence of mobility on deposition temperature shows a strong correlation with the behaviour of the dielectric layers at various temperatures and the diffusion of CuPc molecules.

Light Wavelength Effects on Charge Trapping and Detrapping of AlOx Embedded ZrHfO High-K Stack

When the MOSFET with the SiO2 gate dielectric is scaled down to the nanosize, the leakage current becomes very large and the dopant can easily diffuse to the channel region to degrade the device's performance and reliability [1]. To solve these problems, a physically thicker high dielectric constant (high-k) film with the same equivalent oxide thickness (EOT) as the SiO2 film is used. For the conventional floating gate (FG) memory device, a poly-Si layer is embedded in the silicon dioxide (SiO2) gate dielectric to trap charges. Because of the large band offsets between Si and SiO2, a large operating voltage is required to achieve the acceptable write/erase efficiency and the tunnel oxide layer has to be thick enough to retain the trapped charges [2]. Since the high-k dielectric has lower band offsets with Si than the SiO2 film has, it can be used as the tunnel oxide to solve the above power consumption and charge retention problems. Separately, it has been proved that the Zr-doped HfO2 (ZrHfO) has better bulk and interface properties, such as a higher crystallization temperature, lower interfacial layer thickness, and lower interface density of states, than the undopd HfO2 has [3]. Also, the memory functions of the nc-ZnO or nc-MoOx embedded capacitor are affected by light exposure [4,5]. In this study, MOS capacitors made of the AlOx embedded ZrHfO high-kgate dielectric are fabricated and studied for the light wavelength effects on the memory functions.

Flattening Technique of (551) Silicon Surface Using Xe/H2 Plasma

The interface microroughness between the insulator film and the silicon substrate is one of the critical issues to the gate insulator film reliability and the performance of MOSFETs [1,2]. The atomically flat surface of Si(100) has been obtained by annealing wafers at the temperature of 800 ºC or above [3-7]. The MOSFETs having atomically flat interface between the silicon substrate and the radical gate SiO2 film show higher performances than the MOSFETs having conventional interfaces [3,4,7]. Furthermore, the speed performance of LSI is enhanced by introducing the MOS transistor fabricated on (551) surface silicon substrate [8]. In order to utilize (551) surface silicon substrate, flattening process of (551) silicon surface is required. In this paper, flattening technique of (551) silicon surface are developed by using Xe/H2Plasma.Boron–doped Cz Si(551) wafers (8-12 Ω·cm) were used for the flattening experiment. Before flattening these wafers, the native oxides were removed by 0.5% dilute HF (DHF) and the surface microroughness (Ra) were about 0.12 nm.(I) We applied the flattening technique by the thermal annealing in the ultraclean Ar ambience at the atmospheric pressure. Figure 1 shows 3×3 μm2AFM images of silicon surface after 850 °C annealing for 3 hours. Ra on each terrace of Si(100) surface is 0.03~0.04 nm, which is AFM noise level, and step height has only mono atomic step of 0.135 nm in Fig.1(a). On the other hand, Ra of Si(551) surface is 0.640 nm and step height has a few atomic step in Fig.1(b). Therefore Si(551) surface is drastically roughened by the ultraclean Ar annealing which can flatten Si(100) surface. Figure 2 shows the annealing temperature dependence of Ra of Si(551) surface. With decreasing the annealing temperature from 850 °C to 600 °C, Ra of Si(551) surface is decreased. It is considered that Si atoms on Si(551) surface easily migrate at lower temperature than Si(100). However, atomically flat silicon surface cannot be observed on Si(551) yet.(II) We performed Xe/H2 plasma process at low temperature less than 600 °C in order to flatten Si(551) surface. Figure 3 shows 3×3 μm2 AFM images before and after flattening Si(551) surface by using Xe/H2 plasma. Plasma process was carried out in a microwave-excited high-density Xe (90%)/H2 (10%) mixture plasma at a pressure of 266 Pa at 400 °C for 3 min. Ra of Si(551) surface was decreased by Xe/H2 plasma flattening. Here, Ra of Si(551) surface did not change by annealing in 100% H2 ambient at a pressure of 266 Pa at 400 °C for 10 min without plasma excitation. Therefore it is considered that the surface migration of Si atoms on Si(551) surface increasingly progresses because Si(551) surface became activated by Xe/H2plasma.This work was supported by JSPS KAKENHI Grant Number 22000010. Reference [1] T. Ohmi, et al., Electron. Device Lett., 12, P. 652,1991.[2] T. Ohmi, et al., T-ED 39, P. 537, 1992.[3] R. Kuroda, et al., T-ED, 56, P. 291, 2009.[4] R. Kuroda, et al., Jpn. J. Appl. Phys., 48, P. 04C048, 2009.[5] X. Li, T et al., ECS Trans. 28 (2010) 299.[6] X. Li, et al., Microelec. Eng., 88, P. 3133, 2011.[7] X. Li, et al., Jpn. J. Appl. Phys., 50, P. 10PB05, 2011.[8] T. Ohmi, et al., T-ED, 54. P. 1471, 2007.

Importance of interface engineering for synthesis of SrHfO3 perovskite thin films on Si substrates through crystallization of amorphous films and control of flat-band voltages of metal–oxide–semiconductor capacitors

We studied the crystallization behavior of perovskite SrHfO3 films on Si substrates, which are a candidate for a new gate dielectric film of MOSFETs. It is found that the diffusion of Sr atoms into the Si substrate changes the chemical composition of the film and disturbs the formation of perovskite-type crystals. To overcome this situation, SiN film is demonstrated to be an effective barrier layer. Perovskite-type SrHfO3 crystals are obtained by annealing at higher than 800 °C. The interfacial silicate layer induces a negative flat-band voltage (VFB) shift in MOS capacitors. The importance of a terminating layer for the control of VFB is discussed by comparing with epitaxial perovskite-type crystals.

Experimental Demonstration of Ultrashort-Channel (3 nm) Junctionless FETs Utilizing Atomically Sharp V-Grooves on SOI

Ultrashort-channel junctionless FETs (JL-FETs) were fabricated on silicon-on-insulator substrates utilizing atomically sharp V-shaped grooves produced by anisotropic wet etching. The channel length, defined as the width of the V-groove bottom, was as short as 3 nm, and the channel thickness was between 1 and 8 nm. Excellent transistor characteristics with threshold voltages that are optimal for low-power operation were obtained for both n-FETs and p-FETs when the thickness of both the channel and gate dielectric film thickness was reduced to 1 nm. The origin of the excellent electrostatic control is discussed on the basis of fringe capacitance and quantum confinement effects in a nanometer-scale ultrathin Si layer where band-gap expansion, dielectric constant reduction, and increase in the dopant activation energy become prominent. The electrical characteristics of the ultrashort channel JL-FETs were found to be very sensitive to device parameters such as the channel thickness and dopant concentration.

Electrical characteristics and short-channel effect of c-axis aligned crystal indium gallium zinc oxide transistor with short channel length

A channel length of a c-axis aligned crystal indium gallium zinc oxide (CAAC-IGZO) transistor having low off-state current at a yA/µm level was decreased to 100 nm, and the electrical characteristics and short-channel effect of the CAAC-IGZO transistor were researched. As a result, we found that, in the CAAC-IGZO transistor with L = 100 nm, even with a gate insulator film having an equivalent oxide thickness (EOT) = 11 nm, an extremely small off-state current of 380 yA/µm at 85 °C is maintained, in addition channel length dependence of the electrical characteristics is hardly seen. Favorable values of characteristics of the CAAC-IGZO transistor can be obtained, such as subthreshold slope (SS) = 77 mV/dec, drain induced barrier lowering (DIBL) = 73 mV/V, threshold voltage (Vth) = 0.65 V, and on-state current (Ion) = 65 µA/µm. These results suggest the possibility that the CAAC-IGZO transistor can be applied to an LSI in a deep submicron region.

Temperature Effects on a‐IGZO Thin Film Transistors Using HfO2 Gate Dielectric Material

This study investigated the temperature effect on amorphous indium gallium zinc oxide (a‐IGZO) thin film transistors (TFTs) using hafnium oxide (HfO2) gate dielectric material. HfO2 is an attractive candidate as a high‐κ dielectric material for gate oxide because it has great potential to exhibit superior electrical properties with a high drive current. In the process of integrating the gate dielectric and IGZO thin film, postannealing treatment is an essential process for completing the chemical reaction of the IGZO thin film and enhancing the gate oxide quality to adjust the electrical characteristics of the TFTs. However, the hafnium atom diffused the IGZO thin film, causing interface roughness because of the stability of the HfO2 dielectric thin film during high‐temperature annealing. In this study, the annealing temperature was optimized at 200°C for a HfO2 gate dielectric TFT exhibiting high mobility, a high ION/IOFF ratio, low IOFF current, and excellent subthreshold swing (SS).