Gate Array Research Articles

FPGA simulation of chaotic tent map‐based S‐Box design

AbstractThe chaotic system has a characteristically random behavior by nature, and these systems have their own characteristics in a completely deterministic structure. This feature of a chaotic system makes it difficult to predict encryptions designed based on such a system. Thanks to this unpredictable and strong feature, maps produced from chaotic systems are an important alternative in the field of encryption. One of the structures obtained by employing chaotic maps is the substitution box. S‐Box, which provides the confusion principle used in block ciphers, is the main block that dynamically replaces unencrypted data with confidential data and makes a significant contribution to ensuring high security in the encryption system. Therefore, S‐Boxes hold a critical role in block ciphers. Speed and reliability are important parameters in the creation of this main block. Especially, applications performed on hardware are more reliable and high performance. Therefore, in this study, an S‐Box was designed using field‐programmable gate arrays (FPGA) simulation from a chaotic tent map to create a fast and reliable S‐Box because FPGAs offer solutions that may be important in this field considering their fast and customizable architecture. In the proposed method, the S‐Box was created in 0.16 s. In addition, the dynamic properties of the chaotic tent map were analyzed with Lyapunov exponents, and the NIST SP 800‐22 test was applied for the information encryption suitability of the proposed chaotic system. Also, to test the reliability of the produced S‐Box structures, SAC, non‐linearity, bit independence criteria, and input/output XOR distribution table metrics were implemented. The results showed that the proposed chaotic map was dynamic and passed the reliability tests successfully.

Evaluation and characterization of approximate arithmetic circuits

SummaryWith the end of Dennard's scale, processor designers have been looking for new technical alternatives so that approximate computing (AC) has managed to attract the attention of researchers by offering techniques ranging from the application level to the circuit level. When applying approximate circuits into hardware design, the program user may speed up the application. At the same time, a designer may save area and power dissipation at the cost of less accuracy on the results of operations. This article discusses the compromise between controlled accuracy versus physical efficiency by evaluating a set of arithmetic circuits designs. The article also presents new mixed organization approximate designs. To evaluate the approximate design benefits, we performed a comprehensive set of experiments from tailor‐made approximate arithmetic circuits on field‐programmable gate array and application specific integrated circuits technologies. Our results reveal that our proposed mixed approximate designs have promising results on error rates, area usage, and power dissipation compared to the related work. Another interesting result is that one should care about the prototyping platform where the approximate hardware will be synthesized. Tailor‐made approximate cells may take advantage on intrinsic design details than standard cells or even general prototyping platforms.

A New Hyperchaotic Two‐Scroll System: Bifurcation Study, Multistability, Circuit Simulation, and FPGA Realization

With the swift advancement of chaos theory, the modeling, chaotic oscillations, and engineering applications of chaotic and hyperchaotic systems are important topics in research. In this research paper, we elucidate our findings of a new four‐dimensional two‐scroll hyperchaotic system having only two quadratic nonlinearities and carry out a detailed bifurcation study of the proposed dynamical model. Also, an electronic circuit has been constructed for the new system using MultiSim (Version 14). The implementation of the new 4‐D hyperchaotic system in a field‐programmable gate array (FPGA) is performed herein by applying two numerical methods, viz. Forward Euler Method and Trapezoidal Method. The experimental results show a good match with the simulated hyperchaotic attractors. We also provide details of the hardware resources used for an FPGA Basys 3 Xilinx Artix‐7 XC7A35T‐ICPG236C.

A minimal resource high‐speed routing lookup mechanism for servers with NetFPGAs

AbstractThis paper studies how high‐performance computer servers, equipped with Field‐Programmable Gate Arrays (FPGAs), can perform high‐speed routing. In particular, routing table lookup is considered since it is a key packet processing bottleneck for future routers that need to operate at Petabits‐per‐second. The paper defines and evaluates three routing lookup schemes used by routers/switches, using Xilinx NetFPGA SUME programmable data plane hardware boards. Two existing schemes, namely IP address‐based Longest Prefix Matching and Multi‐Protocol Label Switching tag‐based exact matching are implemented. In addition, the paper presents a new routing scheme called No Lookup Forwarding Scheme (NLFS) that does not use conventional lookup tables. The NLFS approach adds a custom routing tag that does not require any form of (forwarding) table lookup, and independent of the Binary/Ternary Content Associate Memory (CAM) capacity in the switch/router. The experimental results show that the NLFS scheme utilizes less FPGA resources, while reducing packet lookup latency by up to 18% against longest prefix match which is the de facto lookup mechanism used in switches. The key contribution of this work is that it enables the use of NetFPGAs to reduce CAM capacity requirements in switches/routers to help reduce memory costs. The proposed scheme has several use cases, including provision of on‐demand increase of packet routing capacity in data center networks and support for Network Function Virtualization‐based systems.

Efficient hardware‐accelerated pseudoinverse computation through algorithm restructuring for parallelization in high‐level synthesis

SummaryThis paper describes a fast and efficient hardware‐accelerated pseudoinverse computation through algorithm restructuring and leveraging FPGA synthesis directives for parallelism prior to high‐level synthesis (HLS). The algorithm, which is composed of modified Gram–Schmidt QR decomposition (MGS‐QRD), triangular matrix inversion (TMI), and matrix multiplication (MM), is synthesized and implemented on a field‐programmable gate array (FPGA). MGS‐QRD is restructured and augmented with parallelism directives prior to synthesizing the algorithm, which yielded an MGS‐QRD hardware accelerator with high throughput. Modifications to the current TMI algorithm were also proposed, in which the removal of redundant computational tasks was done in order to speed up overall operation. Data dependencies in the MM algorithm were carefully considered such that appropriate parallelism directives were inserted, and matching the data flow of MM with MGS‐QRD and TMI modules was also performed to accelerate the pseudoinverse computation. The results showed that the proposed pseudoinverse module is better than the naïve implementation which is composed of existing MGS‐QRD, TMI and a standard MM in terms of maximum frequency (1.24× speedup), hardware resources(48% of reduction of DSP usage), latency (23% reduction), and throughput (62% increase).

An accelerated architecture of change‐point detection for FMCW radar mutual interference based on FPGA

SummaryThe mutual interference between frequency modulated continuous wave (FMCW) radars seriously affects autonomous driving. The interference will cause a short‐duration pulse‐like signal, which contains several change points in the time domain. The change‐point detection method called bottom‐up segmentation (BOTUP) is applied to deal with a short duration pulse‐like signal, which has excellent detection accuracy. However, the serial processing of BOTUP will cause considerable delay, which is not conducive to real‐time detection of automatic driving. In this paper, an accelerated architecture of BOTUP (ACC‐BOTUP) based on field‐programmable gate array (FPGA) is proposed. As BOTUP has segmented characteristics and without data dependency between the cost functions, a parallel structure is proposed to reduce the latency. Further, a pipeline structure is proposed to execute the operations of the cost functions in an overlapping manner. Compared with the original BOTUP (O‐BOTUP), the latency of ACC‐BOTUP is reduced by 82%, which is more suitable for real‐time detection in autonomous driving.

Hardware Trojan detection for lightweight ciphers implemented on field‐programmable gate arrays using the replay algorithm

SummaryHardware Trojans (HTs) are malicious and intentional modification of the hardware design, embedded by an adversary to leak sensitive data, modify functionality, or cause malfunction. Lightweight ciphers are designed for resource‐constrained devices (RCDs) to balance resources and security, but often targeted by HTs. This work aims to create a trusted lightweight cipher design and detect complex sequential HTs using a runtime monitoring method with minimal resource overhead. The novelty of the approach is that it combines full or partial temporal redundancy, resource minimization, and runtime monitoring. The algorithm employs temporal redundancy, by executing a first run of the cipher, and then replays the cipher fully (ReplayN method) or partially (ReplayN/2 method). A mismatch indicates HT activity, and a third replay is executed to determine the correct results. The ReplayN/2 algorithm further optimizes time and energy by limiting replay to the second half of the cipher rounds. The proposed method is compared with other existing methods including triple modular redundancy (TMR), adapted triple modular redundancy (ATMR), and reverse‐function redundancy (RFR). All methods were implemented in field‐programmable gate array (FPGA) technology. Implementation performance metrics were measured and compared, including resource utilization (i.e., logical elements [LEs]), power, energy (E), and speed (i.e., Fmax). The results show that the proposed algorithm outperforms existing methods in most of the metrics. In terms of speed and area, the replay algorithm is faster by 24% and reduces total LEs by 42% when compared with existing methods. Regarding power, replay algorithm reduces power by 45% when compared with TMR and ATMR. With respect to energy, replay methods reduce energy by an average of 6% when compared with TMR and ATMR. The ReplayN/2 reduces energy by an average 15% when compared with TMR and ATMR. Based on the (i.e., energy × area) metric, ReplayN/2 is the top performing method as it balances area and energy metrics. Using metric, the replay methods are the best performing methods as they best balance area, energy, and speed. Also, based on metric, the replay methods are the top performing methods.

Performance analysis of novel fault‐tolerant multilevel inverter with a pristine methodology for fast and exhaustive real‐time failure of switches

SummaryMultilevel inverter (MLI) provides a high power density, though the number of devices increases the chances of failures increases, reducing the reliability of power converter. It is essential to detect, isolate, and reconfigure the faults which arises in MLI. The research proposed here is capable of accomplishing the complete fault tolerance against single and multiple devices for both open circuit and short circuit faults. The control algorithm for operation of single‐pole‐double‐throw (SPDT) relays. This methodology is capable of completely preserving the normal operating condition in post‐fault condition also. The output voltage waveform matches by voltage sensors connected across load, and the controllers sense the faults originated from the variation in the look‐up‐table (LUT) and also categorize the nature of the faults. Field‐programmable gate array (FPGA)‐based controller sends a command signal through SPDT to isolate the faulty switches by redundant switches. In this way, the output power across the load is preserved. This research article also covers the comparative study that is made with the existing fault‐tolerant structures. The reliability comparison shows the better performance indices over conventional cascaded H‐bridge (CHB) inverter. The simulation and experimental results validate the effectiveness of control methodology to achieve complete fault tolerance.

Reconfigurable field‐programmable gate array‐based on‐chip learning neuromorphic digital implementation for nonlinear function approximation

SummaryHardware implementations of spiking neural networks, which are known as neuromorphic architectures, provide an explicit understanding of brain performance. As a result, biological features of the brain may well inspire the next generation of computers and electronic systems used in such areas as signal processing, image processing, function approximation, and pattern recognition. Approximating nonlinear functions has many uses in computer science and applied mathematics. The sigmoid is the most universal activation function in neural networks by which the relationship between biological and artificial neurons is defined. It is a suitable option for predicting the probability of anything from 0 to 1 as output. In this paper, a spiking neural network using Izhikevich neurons and a gradient descent learning algorithm are propounded to approximate the sigmoid and other nonlinear functions. The flexibility of the spiking network is demonstrated by showing the average relative errors in the approximation process. A time‐ and cost‐efficient digital neuromorphic implementation on the base of on‐chip learning method for approximating the sigmoid function is also discussed. The paper reports the results of the hardware synthesis and the spiking network's physical implementation on a field‐programmable gate array. The maximum frequency and throughput of the implemented network were 83.209 MHz and 9.86 Mb/s, respectively.

Dead‐Time Elimination PWM with Switching Times Sharing for H Bridge Inverter

In this paper, the novel on‐off modes including 12 conduction states is presented for H bridge in one switching period. Based on the novel on‐off mode, the dead‐time elimination pulse width modulation (PWM) is presented with good switching times sharing effect. The digital judgment method of output current polarity is proposed for the dead‐time elimination PWM. The PWM generator is integrated in the field‐programmable gate array. Simulation and experimental results are provided to validate that the proposed PWM can be applied to H‐bridge voltage source inverter with good performance. © 2021 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.

A new hardware architecture of the adaptive vector median filter and validation in a hardware/software environment

SummaryPresented in this paper is a new hardware architecture of the adaptive vector median filter (AVMF). The suggested structure yielded important values in impulsive noise removal from color images while preserving their fine details. The software (SW) study of this filter demonstrated that its implementation is too complex. To overcome this limitation, some approximations using a ROM memory were proposed to perform the square root for a hardware (HW) implementation. Comparative results between the ideal and approximated SWs of the AVMF showed a relative error equal to 0.01%. Then, sequential and parallel HW architectures were developed for this filter based on the approximated method. Finally, the validation of these architectures was conducted using an field‐programmable gate array (FPGA) platform on an HW/SW environment. The validation results demonstrated that the proposed HW/SW implementation of the AVMF can speed up the execution time 180 times in the worst case at 140 MHz compared to the SW solution as well as preserving a high data quality (same image quality).

Experimental investigation on the control strategy of split source inverter for grid‐connected wind power generation system

AbstractThe utilization of an impedance network in power electronic applications overcame traditional two‐stage converters' drawbacks, including a dc‐dc and dc‐ac stage. A well‐designed impedance‐based converter shuns the necessity of multiple network stages that, in turn, enhance operational performance and reliability. The split source inverter (SSI) belongs to such a single‐stage system that consists of an impedance network with a voltage source inverter. The work's primary purpose is to explore the performance of grid‐connected SSI in the application of wind energy systems. A novel peak power tracking controller is proposed for the SSI‐based wind energy systems for tracking the maximum power available in the wind. The grid‐side controller's current regulator is modified to sense the intermittent wind's perturbation and to regulate the SSI output current. The theoretical analysis is validated by simulation, and different case studies are analyzed by considering the mutual effects of SSI and variable wind speed. A laboratory prototype is designed for the experimental investigation of the SSI that consists of a 5‐kVA three‐phase grid‐tied SSI and wind emulator prototype. A field‐programmable gate array (Xilinx) is used to program the control algorithm. Different test cases are analyzed experimentally to prove the robustness of the proposed controller.

Field‐programmable gate array‐based design for real‐time computation of ensemble empirical mode decomposition

SummaryEmpirical mode decomposition (EMD) is considered as a suitable method when the signal to be analyzed is nonlinear or nonstationary in nature. But, EMD suffers from a problem known as mode mixing. To, reduce this problem, ensemble EMD (EEMD) was proposed. In this paper, we have presented a fast field‐programmable gate array (FPGA)‐based design for EEMD. Where calculation of output can be done in a parallel manner for different realizations. The design has a comparatively less execution time, and the execution time of the proposed EEMD design is even less than some state‐of‐the‐art EMD‐based design, although the architecture of EEMD is more complex, when compared with the EMD design. In this work, we have also performed an FPGA implementation of the EMD algorithm. The root mean square error (RMSE) and the correlation values of the intrinsic mode function (IMFs) obtained from the proposed EMD and EEMD designs are compared. The proposed FPGA‐based architecture of the EEMD algorithm is designed using Verilog‐hardware description language (HDL) and implemented on a Kintex‐7 FPGA. The EEMD architecture consists of cubic Hermite spline interpolation (CHSI) and cubic spline interpolation (CSI) for the envelope generation.

Development of a cost‐effective circuit hardware architecture for brushless direct current motor driver

SummaryA dual‐duty digital pulse‐width modulation (DDPWM) technique‐based cost‐effective control hardware architecture for brushless DC (BLDC) motor drive is reported in this paper. DDPWM control technique involves reduced computational complexity, which is beneficial in on‐chip area and power dissipation reduction. Simple Hall sensor‐based speed calculation and commutation circuits were also incorporated in the hardware to reduce the chip area further. The edge detection‐based speed calculation circuit was designed to be tolerant of any external noise or glitch in the Hall sensor signal. The proposed hardware architecture was implemented on the field‐programmable gate array (FPGA) and application‐specific integrated circuit (ASIC) platform using TSMC 180‐nm technology library. The ability of the integrated circuit (IC) for resource utilization reduction was validated by comparing the FPGA‐implemented architecture with the existing literature. The FPGA‐implemented architecture was also examined in real‐time using an experimental prototype BLDC motor setup. The drive response with dynamic load and speed variations, speed control precision, and glitch tolerant speed calculation is reported in the paper. The ASIC implementation demonstrates that the developed architecture sampled at 50 MHz is highly effective in the gate count and power dissipation reduction compared to the standard PI controller‐based width modulated pulse generation hardware architecture.

A real‐time touch control system design based on field‐programmable gate array via optimizing Bresenham algorithm for electrowetting displays

AbstractElectrowetting displays (EWDs) have the advantages of fast response speed and extremely low energy consumption. However, the function of real‐time touch control has not been realized in EWDs, and the rendering of hand‐drawn lines by a pixelated display has room for improvement, especially in the diagonal directions. The issue of clearly rendering diagonal lines drawn by touch control is not specific to EWDs, and the solution we offer can be beneficial to other display technologies. In this paper, a real‐time touch control system, which was based on field‐programmable gate array (FPGA) by optimizing Bresenham algorithm, was realized in EWDs. In hardware, Nios II processor was used as a main controller, I2C bus communication mode was used to establish a communication between a touch screen and the main controller, and MXEI1480 and MXEI2240 were used as driving chips to complete the design of EWD driver module. In software, Bresenham algorithm was optimized to add pixel points at diagonal corners for improving the clarity of line rendering. Then, touch coordinates were transmitted to the EWD driver module for displaying lines rendered. Experimental results showed that the lines rendered on the display by the optimized Bresenham algorithm were thicker and clearer.

Co‐design implementation of High Efficiency Video Coding standard encoder on Zynq MPSoC

SummaryStatistical analysis of High Efficiency Video Coding (HEVC) encoder reveals that in the motion compensation block, the interpolation filter consumes more than 30% in the encoder time in comparison with other blocks. In this paper, we start with an optimized hardware implementation of the interpolation filter on field‐programmable gate array (FPGA) based on Xilinx setup environment. In a second step, a Hardware/Software (HW/SW) co‐design implementation of HM16.7 encoder is performed on Zynq MPSoC platform to evaluate the proposed interpolation filter IP in terms of total encoder run‐time, taking advantages of both processing units (quad‐core ARM Cortex TM‐A53 processor and Programmable Logic FPGA component) available on the Zynq MPSoC. The proposed architecture of luma and chroma filters was simulated and synthesized on Xilinx XCZU7EV‐2FFVC1156 FPGA at 250‐MHz clock frequency. The synthesis results present an optimized power consumption of 3.308 mW for higher resolutions (2560 × 1600 and 1920 × 1080) at 50 fps with the use of just 1% of the FPGA resources. The experimental results of the co‐design implementation of HEVC encoder present a speedup of 2 times (41% in PeopleOnStreet sequence) in terms of processing time compared to the software alone implementation, with a an increase of 0.51% of bit rate and a very small degradation of peak signal‐to‐noise ratio (PSNR) (0.01%).

Solar powered Modified Coupled Inductor, Capacitor Multiplier boost converter operated three‐phase small power inverter

AbstractThe solar power generation system is being increasingly connected to the low power distribution system due to its low cost and abundant availability. The interconnection of the solar power generation system demands new and efficient power converters to provide sufficient boost factor for the solar panel output voltage. This paper presents a Modified Coupled Inductor, Capacitor Multiplier (MCICM) direct current (DC)–DC boost converter to provide high boost factor for the solar panel output voltage and to maximize the benefits of the grid‐interfacing three‐phase three‐wire inverter. The fuzzy logic‐based DC‐link voltage controller and hysteresis current controller (HCC) are also proposed to enhance the power transfer ability of the small power grid‐connected inverter. The new topology of boost converter constructed with the coupled inductors, capacitor, and high‐frequency transformers is demonstrated through the series of tests carried out with extensive MATLAB/Simulink simulation studies. The SPARTAN 3 field‐programmable gate array (FPGA)‐based prototyping model validated the performance of the proposed topology, experimentally.

Programmable Controls to Scattering Properties of a Radiation Array

AbstractElectromagnetic (EM) waves have been widely applied in wireless communications, radar detection, navigation, and target recognition. Radiation and scattering are two common behaviors in the EM community, but it remains a long‐standing challenge to control them in a dynamical way, especially using a single, low‐cost, and compact hardware. Here, a promising solution is proposed by combining a programmable metasurface with a radiation array, which can manipulate the scattering properties, digitally and in real‐time, and exhibit different radiation modes simultaneously. More advantageous over previous investigations with the fixed radiation‐scattering performance, a field‐programmable gate array is introduced to extend, realize, and verify the multiple functions of the meta‐microstructure (MMS). As a proof‐of‐concept, multiple functions, including polarization conversion, scattering beam manipulation, diffusion scattering, radar cross‐section reduction, EM waves radiation, and vortex beam generation, have been adequately demonstrated by the MMS prototype.

BPSK Modulation‐Based Local Oscillator‐Free IQ Demodulation for Millimeter Wave Imaging

The precision of local oscillator (LO) signal in in‐phase and quadrature (IQ) demodulation strongly affects the imaging performance of millimeter wave (mmWave) radars. Therefore, to eliminate the requirement for high‐precision LO, a simple yet effective digital IQ demodulation method has been proposed with the aid of a specified sampling scheme in order to eliminate the demand for LO. Based on the bandpass sampling theorem, the characteristic of the intermediate frequency signal of mmWave imaging indicates that the LO is unrequired if the sampling rate is twice of the frequency of the carrier of the intermediate signal. In this way, the in‐phase signal would be directly and accurately obtained by performing the Binary‐Phase‐Shift‐Keying (BPSK) modulation on the samples, based on which the IQ demodulation would be completed by using the Hilbert transform. The proposed method does not employ LO and thus simplifies the demodulation process and is suitable for implementation in a Field‐Programmable Gate Array (FPGA) with fewer hardware resources. To verify the method, a three‐dimensional mmWave radar imaging is carried out at the 30‐34 GHz bandwidth, where the sampling and digital IQ demodulation are realized by an ADC (AD9250) and FPGA (XC7K325T), respectively. The results show a simplified transceiver with lower requirements and the prospect of the proposed method being applied in radar imaging and other related fields.

RETRACTED: Forest park landscape pattern system based on FPGA and GIS system

Perceptual scenes and scene swing surveys are the ideas for reminding local and wooded area park executives and scene placement. The maximum precise analysis of panorama visualization, forest park landscapes, planning of essential scenic spots, and visualization and safety of Geographic Information Systems (GIS) cost tools is primarily based on management and historical data. Visual impacts and cultural, historical past adjustments to are expecting visual and natural landscapes. By deciding on points from a panorama attitude, intervention calls for vital signs and symptoms of safety. Among them, studies are being carried out in many towns around the arena. Geographic Information System (GIS) depends simply on noticeable assessment and is remembered for the social legacy plan. The Gate Array (FPGA) and Geographic Information System (GIS) are analyzed based on the panorama in every place within the painting's framework. In these activities, landscape planning is proposed thru the development of scientific Piedmont. Turin is conducting a few research. From a global attitude, the version suggests that these packages reduce the capability use of the era.