GaAs LSI Research Articles

20.8 Gb/s GaAs LSI self-routing switch for ATM switching systems

An 8/spl times/8 self-routing hardware switch providing 20.8 Gb/s throughput has been developed for asynchronous transfer mode (ATM) switching systems. The basic architecture of this switch is a Batcher-Banyan network. A new mechanism for data processing and distributing high-speed signals is proposed. This switching system consists of three LSIs using a 0.5-/spl mu/m gate GaAs MESFET technology. These LSIs are a switching network LSI for exchanging packet cells with eight cell channels, a negotiation network for screening of cells destined for the same output port, and a demultiplexer LSI for converting the cell streams from the switching network LSI to the eight streams per channel. These LSIs are mounted in a 520-pin multichip module package. The total number of logic gates is 13.3 k, and the power dissipation is 24 W. The switching system fully operates at a data rate of 2.6 Gb/s, and its throughput is 20.8 Gb/s.

A 2.5 Gb/s ATM add-drop unit for B-ISDN based on a GaAs LSI

This paper describes the design and implementation of a high-speed GaAs asynchronous transfer mode (ATM) mux-demux ASIC (AMDA) which is the core LSI circuit in a high-speed ATM add-drop unit (ADU). This unit is used in a new distributed ATM multiplexing-demultiplexing architecture for broadband switching systems. The ADU provides a cell-based interface between systems operating at different data rates (the high-speed interface being 2.5 Gb/s and the low-speed interface being 155/622 Mb/s), or can be used for building local high-speed switches and LANs. Self-timed first-in-first-out (FIFO) buffers are used for handling the speed gaps between domains operating at different clock rates, and a self-timed at receiver's input (STARI) interface is used at all high-speed chip-to-chip links to eliminate timing skews. A printed circuit board (PCB) with two ADUs in a distributed multiplexing-demultiplexing architecture has been developed, and the AMDA demonstrated operation above 4 Gb/s (500 MHz clock frequency) with an associated power dissipation of 5 W in a standard 0.8 /spl mu/m E/D MESFET process.

Asynchronous transfer mode switching LSI chips with 10-Gb/s serial I/O ports

LSI chips were developed that fit on a switching fabric using chip-to-chip optical interconnections; they have 10-Gb/s serial input and output ports, which facilitates the layout of optically interfaced switching element modules. A test switching module composed of these chips was operated at 10.2 Gb/s without bit errors. Ultrahigh-speed switching LSI chips have been developed for a future asynchronous transfer mode (ATM) switching system with an over-Tb/s capacity. Their serial input and output ports facilitate chip-to-chip optical interconnection. Cell-dropper and crosspoint-router LSI chips, composing the core of the switching element, were fabricated by using GaAs LSI technology. A test switching module composed of these chips was operated at 10.2 Gb/s without bit errors. >

Future Ultra-Large Scale Integration: Transport Physics in Semiconductor Nanostructures

The progress in Si ULSI, and the parallel progress in GaAs LSI, has pushed the gate length in current devices toward 0.1 µm. Research laboratories have gone even further, and FETs with gate lengths as short as 20 nm have heen demonstrated. It is apparent that within the next decade or so, devices with gate lengths approaching this scale will be made in the production environment. These devices are likely to be susceptible to new physical effects that are now being studied in nanostructures, or mesoscopic devices as they are usually called. The first new effect, already seen in the short-gate length devices, is tunneling through the gate depletion region. In this paper, we try to summarize the major physical effects, some approaches to studying them, and the role they may play in future industrial devices.

Highly reliable Au-Sn eutectic bonding with background GaAs LSI chips : Masanori Nishiguchi, Noboru Goto and Hideaki Nishizawa. IEEE Trans. Compon. Hybrids mfg Technol.14(3), 523 (1991)

Highly reliable Au-Sn eutectic bonding with background GaAs LSI chips : Masanori Nishiguchi, Noboru Goto and Hideaki Nishizawa. IEEE Trans. Compon. Hybrids mfg Technol.14(3), 523 (1991)

A 2.5 ns 8×8-b parallel multiplier using 0.5 μm GaAs/GaAlAs heterostructure field effect transistors

To increase performance of GaAs LSI digital circuits, a 0.5 μm recessed gate process has been developed and utilized for an 8×8-b parallel multiplier. The chip contains about 3000 heterostructure field effect transistors and has a power consumption of 1.5 W. The best results of the maximum multiplication time measured were below 2.5 nsec.

A high yield buried p-layer fabrication process for GaAs LSI circuits

GaAs MESFETs for LSI and VLSI require high transconductance to drive large wiring loads, but they must also exhibit extremely good uniformity and reproducibility. To provide ion-implanted MESFETs that meet these conflicting needs, the authors developed a 0.7- mu m buried p-layer (BP) multifunction self-aligned gate (MSAG) fabrication process which has demonstrated excellent yields for circuits of up to 5000 gates. Device and circuit performance has been studied as a function of BP implant dose. LSI circuit yield and performance have been characterized using 4*4-, 8*8-, 12*12-, 16*16-, and 20*20-bit parallel-array multipliers on the same die. A high-dose BP implant has resulted in sigma V/sub T/ as low as 8 mV over 3-in wafers and 20*20-bit multipliers with self-test yields of 61%. Measured worst-case multiplication times range from 870 ps for the 4*4-bit to 6.5 ns for the 20*20-bit multipliers, representing record speeds for these multipliers. The average gate delays for these multipliers are 51 to 67 ps, the fastest extracted gate delays reported for LSI circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Signal analysis of a GaAs 1K-SRAM by high-speed e-beam testing

This paper reports on the internal signal analysis of a GaAs 1K-SRAM by means of a high-speed e-beam test system developed in our laboratories. It allows noninvasive measurements on signal lines within the circuit with a very high spatial resolution (spot diameter: 0.5 μm) and a delay time resolution better than 3.5 ps. With this technique, it is possible for the first time, to our knowledge, to directly measure internal high-frequency signals of a GaAs LSI circuit, thus obtaining information which is inaccessible by other measurement techniques and allowing an extensive circuit analysis. For example, a measured time budget for the memory could be obtained. Furthermore, the comparison between measured and simulated waveforms enables the designer to directly evaluate the accuracy of the transistor and signal-transmission line models. The waveform measurements on the bit lines during the read process and inside an address buffer of the memory were analysed.

High mechanical reliability of back-ground GaAs LSI chips with low thermal resistance

GaAs LSI-sized 6.35 mm square chips with mirror ground back surfaces (Rmax=0.1 mu m) have been confirmed to be almost as reliable as chemically thinned ones through fracture stress experiments. Two fracture strength test methods, the four-point bending test and the biaxial tension test, were performed and the data were analyzed based on Weibull statistics. The 1 mu m post-grinding chemical etching in the original wafer thinning technology was proven to be effective in eliminating the surface flaws due to grinding, which act as stress concentrators and reduce mechanical strength. The thermal resistance of back-ground 5 mm square GaAs chips was observed to be low by utilizing the surface temperature measurement technology based on the diode drop technique. The thermal resistance was judged to be independent of the back-surface treatment.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Highly reliable Au-Sn eutectic bonding with background GaAs LSI chips

The authors investigate the reliability of mechanically ground chips through die-shear and thermal shock tests. The bonded chips, which were ground to 450 mu m thickness by an original technology, were proved to be as reliable as polished chips through 1000 cycles of thermal shock between -65 degrees C and +150 degrees C. No chip fracture occurred and no induced void was observed with scanning acoustic microscopy. The shear strength of the chips after thermal shocks remained at more than 10 kg, passing the MIL-STD-883C test. Surface flaws due to backgrinding, which would cause chip fracture, were eliminated by the slight chemical etching after backgrinding. Scrubbing action has been confirmed to be necessary to obtain void-free bondings consistently in low-cost production. The Sn in the Au-Sn preform easily forms on oxide film at the surface, which tends to prevent wetting at the bonding interface. This tin oxide film (300-400 AA) was observed through Auger electron spectroscopy (AES) to be broken down by scrubbing action. >

A 1.5 Gbit/s GaAs four-channel selector LSI with monolithically integrated newly structured GaAs ohmic contact MSM photodetector and laser driver

A monolithic integrated 1.5 Gb/s high-speed four-channel optoelectronic integrated circuit (OEIC) selector GaAs LSI circuit is discussed. This LSI circuit incorporates photodetectors, preamplifiers, a selector, a decision circuit, and a high-speed laser driver. To achieve high efficiency, a AuGe/Ni-GaAs structured ohmic contact metal-semiconductor-metal (OC-MSM) is used for the interdigitated structural photodetector. With this OC-MSM structure, photocurrent is approximately twice as effective as with the conventional Schottky contact MSM structure. The new LSI has a maximum operating speed of 1.5 Gb/s and exhibits low power dissipation of 927 mW. >

Annealing technology under arsenic overpressure for GaAs LSI — influence on dislocation and threshold voltage: T EGAWA, Y SANO, H NAKAMURA, K KAMINISHI (Res. Lab.. Oki Electr. Ind. Co. Ltd., Hachioji, Japan) Electron. Commun. Jpn. 2. Electron. (USA), vol. 71, no. 4, pp. 10–18 (April 1988)

Annealing technology under arsenic overpressure for GaAs LSI — influence on dislocation and threshold voltage: T EGAWA, Y SANO, H NAKAMURA, K KAMINISHI (Res. Lab.. Oki Electr. Ind. Co. Ltd., Hachioji, Japan) Electron. Commun. Jpn. 2. Electron. (USA), vol. 71, no. 4, pp. 10–18 (April 1988)

Application of a 3000-gate GaAs array in the development of a gigahertz digital test system

The characterization of a high-speed GaAs LSi gate array and its personalization as the central control chip for a gigahertz-rate digital test system are described. The array is a 1020-configurable-cell, 3000-gate device that utilizes a commercially available enhancement/depletion (E/D) mode IC process. The development and experimental evaluation of an array personalization designed to characterize all logic macros, the array speed-power performance, and a simple MSI arithmetic element are described. The results of the evaluation of this first design were used to design a digital tester control chip for use at clock rates of up to 1 GHz. Issues in the design of a digital tester are outlined, and the architectural features of a modular tester providing synchronous data acquisition, high-speed RAM control, and pattern generation are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Annealing technology under arsenic overpressure for GaAs LSI–influence on dislocation and threshold voltage

AbstractSince the microscopic uniformity of the threshold voltage (Vth) of an FET is important to obtain GaAs LSI, the cause of the threshold voltage uniformity was researched by investigating the annealing dependencies of the dislocations in the semiinsulating substrate of LEC GaAs and the microscopic uniformity of Vth. Annealing under arsenic overpressure decreased the dislocation density on the substrate surface and formed a uniform distribution of dislocations. This is believed to be caused by the supply of arsenic to the substrate surface. When annealing was carried out under low arsenic pressure, Vth shifted toward the negative direction at the area with clustered pits, and a clear dislocation network was formed. On the other hand, when annealing was carried out under arsenic overpressure using arsene, the shift of Vth in a negative direction becomes small and Vth was distributed uniformly. When annealing was carried out using a protective PCVD SiNx film, the distribution of Vth was consistently uniform, regardless of the dislocation distribution. As described in the preceding, it was found that a high concentration of AsGa exists in the area of the clustered pits, the uniformity of Vth is independent of the dislocation density but dependent on the stoichiometry of the substrate prior to or after annealing, and the distribution of Vth becomes more uniform with an increase of arsenic concentration.

Advantages of metallic-amorphous-Silicon-gate FET's in GaAs LSI applications

A Schottky barrier as high as 1 V is obtained for contact between a ternary amorphous film, a-Si-Ge-B, and an n-type GaAs crystal. A metallic-amorphous-silicon-gate FET (MASFET) was made using the amorphous film as a gate contact. GaAs MASFET characteristics are superior to GaAs MESFET characteristics in application to LSI's with a DCFL configuration because the DCFL circuits with the GaAs MASFET's provide a logic level as high as 0.94 V and widen the circuit operation margin. Full operation is obtained from a 1 Kword × 2 bit SRAM with GaAs MASFET's, which is considered to be mainly due to the wide operation margin. The measured propagation delay time of the DCFL inverter is 34 ps at supply voltage V_{DD} = 1.5 V and power consumption of 1.9 mW/gate.

Monolithic GaAs photoreceiver for high-speed signal processing applications

High-speed planar monolithically integrated GaAs photoreceivers have been fabricated by selective ion implantation into SI GaAs substrates. Their fabrication is fully compatible with existing GaAs LSI process schedules. A receiver upper cutoff frequency of 1.5 GHz and sensitivity of 112 V/W have been measured. The application of these devices in short-haul high-bit-rate data communication systems has been demonstrated in a 560 Mbit prototype optical data link, using packaged and fibre-coupled devices.

High-Speed Time Switch Using GaAs LSI Technology

A high-speed time switch using GaAs LSI technology is discussed. A new high-speed time switch structure consisting primarily of shift registers is proposed. This structure requires relatively minimal hardware in designing LSI. As the first stage of study, a GaAs 4-channel time switch LSI is manufactured using this structure. Switching speed of the LSI is 2 Gbits/s and the power consumption 0.64 W/chip. Largecapacity switch configurations using this time switch are proposed. This high-speed time switch makes possible the time-division switching of such services as T.V. and high-definition T.V.

Buried p-layer SAINT for very high-speed GaAs LSI's with submicrometer gate length

A new SAINT FET with a depleted p-layer buried under the active layer has been developed in order to make very high-speed GaAs LSI's with submicrometer gate lengths. The p-layer design has successfully suppressed the substrate current that causes the serious short-channel effects in an n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> self-aligned (SAINT) MESFET. Since the whole p-layer, formed by Be ion implantation, is depleted by the built-in potential against the upper n-channel layer, it does not lead to a parasitic capacitance increase. The impurity concentration of the player has been limited to optimize operation speed. The alleviation of the short-channel effects combined with the reduction of effective channel thickness has increased the drain current by a factor of about 2 and decreased the propagation delay time of the ring oscillator by a factor of 1.6. A maximum transconductance of 420 mS/mm and a minimum delay time of 9.9 ps/gate have been obtained at room temperature.

Fully Decoded GaAs 1-kbit Static RAM Using Closely Spaced Electrode FET's

This paper describes the design, fabrication, and performance for a low-power high-speed GaAs 1-kbit static RAM. In order to reduce the power dissipation, low current loads have been used in the memory cells and E/D type direct-coupled FET logic (DCFL) circuits have been employed for the peripheral circuits. The high-speed performance has been obtained by suppressing the voltage swings at bit lines having large interconnection capacitances. An address access time of 6.2 ns has been obtained with a very low power dissipation of 20.2 mW. The obtained 125-pJ access time-power dissipation product is the smallest in the GaAs 1-kbit static RAM's that have been reported. The minimum address access time has been 4.8 ns for the power dissipation of 93.8 mW. Our GaAs LSI processing technologies, including the closely spaced electrode FET fabrication technology, have made it possible to achieve a complete operation in the DCFL circuit GaAs LSI with a small voltage swing.

A GaAs 1-kbit static RAM with a shallow recessed-gate structure FET

A novel GaAs FET structure, the shallow recessed-gate structure, has been proposed and applied to a 1-kbit static RAM. In order to decrease the source resistance R s and gate capacitance C g , the shallow n+implanted layer was formed between the gate and source/drain region; then the gate region was slightly recessed. This FET has a high transconductance g m , low source resistance R s , small gate capacitance C g , and small deviation of threshold voltage \part V_{th} , and thus is suitable for high-speed GaAs LSI's. A 1-kbit static RAM has been designed and fabricated applying this FET structure and an access time of 3.8 ns with 38- mW power dissipation has been obtained.