Fully Decoded GaAs 1-kbit Static RAM Using Closely Spaced Electrode FET's

Abstract

This paper describes the design, fabrication, and performance for a low-power high-speed GaAs 1-kbit static RAM. In order to reduce the power dissipation, low current loads have been used in the memory cells and E/D type direct-coupled FET logic (DCFL) circuits have been employed for the peripheral circuits. The high-speed performance has been obtained by suppressing the voltage swings at bit lines having large interconnection capacitances. An address access time of 6.2 ns has been obtained with a very low power dissipation of 20.2 mW. The obtained 125-pJ access time-power dissipation product is the smallest in the GaAs 1-kbit static RAM's that have been reported. The minimum address access time has been 4.8 ns for the power dissipation of 93.8 mW. Our GaAs LSI processing technologies, including the closely spaced electrode FET fabrication technology, have made it possible to achieve a complete operation in the DCFL circuit GaAs LSI with a small voltage swing.