Direct Coupled FET Logic (DCFL) circuit for GaAs LSIC application

Abstract

Direct Coupled FET Logic circuit (DCFL) has a simple structure and high speed with very low power dissipation. It is the most widely used for high density GaAs digital integrated circuits at the time. Nevertheless, the conventional E/D DCFL has some disadvantages like small noise margin, difficult fabrication process, sensitivity to temperature shifts and low yield. This paper describes E/D super buffer logic and E/E mode logic. The DC, transient and temperature performance are studied and compared. The E/D and E/E DCFL circuit was fabricated using a 1 /spl mu/m TiPtAu recess gate process. The minimum value of propagation delay time with fan-out of one is 56 ps and 83 ps for E/D and E/E logic respectively. Through the temperature test from -50/spl deg/C to 100/spl deg/C, it was found that E/E logic has a better temperature performance over E/D logic and has improved yield.