We have undertaken a systematic study of silicon incorporation on planar and patterned GaAs substrates. In this paper we link the observed electrical characteristics of lateral p - n junctions formed on patterned (100) and (110) substrates to silicon incorporation on the chosen surfaces and subsequent defect formation. Lateral p - n junctions were fabricated on patterned (100) and (110) substrates. These were located at the upper and lower boundaries between the (100) - (311)A and (110) - (100) flat - facet combinations. Electrical measurements revealed two main current mechanisms, dominant over separate sections of the voltage characteristic. Under low bias, a tunnel current was observed in all samples and this was ascribed to indirect electron tunnelling into band-tail states, followed by recombination via phonon emission. The magnitude of the excess current in various junction combinations was observed to be related to the degree of compensation in the junction regions, determined by the growth conditions and Ga migration effects; the highest levels were measured in the most compensated material. Recombination and diffusion currents were dominant under high bias conditions. The value of the ideality factor was found to be dependent on the relative magnitudes of the majority carrier densities on either side of the depletion region.
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