Fully Depleted Research Articles

Gate Length and Gate Width Dependence of Drain Induced Barrier Lowering and Current-Onset Voltage Variability in Bulk and Fully Depleted Silicon-on-Insulator Metal Oxide Semiconductor Field Effect Transistors

This paper presents the statistical analysis of a newly found drain current variability component called “current-onset voltage” (COV) variability as well as drain induced barrier lowering (DIBL) variability in bulk and fully-depleted (FD) silicon-on-insulator (SOI) devices. Intensive variability measurement data show that gate length and gate width dependent COV variability and DIBL variability in bulk metal–oxide–semiconductor field effect transistors (MOSFETs) deviate from the straight line in the Pelgrom plot. On the other hand, COV variability and DIBL variability in FD SOI MOSFETs fall on the straight line. Their mechanisms are discussed based on three-dimensional (3D) device simulation considering random dopant fluctuation (RDF). It is found that the saturation of the COV and DIBL variability in smaller devices is caused by weaker averaging effect of channel potentials.

Analytical Model of Subthreshold Current and Threshold Voltage for Fully Depleted Double-Gated Junctionless Transistor

In this study, we derive an analytical model of an electric potential of a double-gated (DG) fully depleted (FD) junctionless (J-less) transistor by solving the two-dimensional Poisson's equation. On the basis of this two-dimensional electric potential model, subthreshold current and swing can be calculated. Threshold voltage roll-off can also be estimated with analytical forms derived using the above model. The calculated results of electric potential, subthreshold current and threshold voltage roll-off are all in good agreement with the results of technology computer aided design (TCAD) simulation. The model proposed in this paper may help in the development of a compact model for simulation program with integrated circuit emphasis (SPICE) simulation and in providing deeper insights into the characteristics of short-channel J-less transistors.

Suppression of Within-Device Variability in Intrinsic Channel Tri-Gate Silicon Nanowire Metal–Oxide–Semiconductor Field-Effect Transistors

In this paper, the variabilities of threshold voltage (VTH), drain-induced barrier lowering (DIBL), and current onset voltage (COV) in intrinsic channel silicon nanowire metal–oxide–semiconductor field-effect transistors (MOSFETs) were evaluated and compared with those of conventional bulk and fully depleted (FD) silicon-on-insulator (SOI) MOSFETs. The random component of variability is extracted by a “within-device” variability method to exclude the systematic component. It is found that the within-device variabilities of DIBL and COV as well as VTH are extremely small in intrinsic channel nanowire MOSFETs owing to the non-intentionally doped channel and small gate workfunction variability. The intrinsic channel nanowire MOSFET is promising for a future scaled device structure in terms of not only the short channel effect suppression but also the variability suppression.

A Subthreshold Current Model of Fully-Depleted Silicon-on-Insulator Metal–Oxide–Semiconductor Field Effect Transistors with Vertical Gaussian Profile

A subthreshold current of fully-depleted (FD) silicon-on-insulator (SOI) metal–oxide–semiconductor field effect transistors (MOSFETs) with vertical Gaussian profile is presented in the paper. The model is based on analytical approximated solution of two-dimensional Poissons' equation and Boltzmann transport equation. The front and the back channel currents are effectively derived using a novel inversion layer model and the boundary conditions which take the nonuniform doping into account. The results are matched well with the numerical simulation results obtained by Sentaurus Technology Computer-Aided Design (TCAD). The model is believed to provide a deep physical insight and understanding of FD-SOI MOSFETs with a non-uniform doping profile operating in the subthreshold regime.

Analog image recognition arrays design by using co-fabricated MOSFET and MESFETs on a 0.25 μm SOS process

This paper presents an analog image recognition system with a novel MESFET device fabricated on a fully depleted (FD) CMOS process. An analog image recognition system with a power consumption of 2.4 mW/cell and a settling time of 6.5 μs was designed, fabricated and characterized. A CNN is employed to realize a core cell of the proposed image recognition system. While a CNN benefits from its regular structure, it faces challenges due to its power consumption, speed, and size in their CMOS implementations. SOS MESFETs can deal with the challenges associated with CMOS-based CNNs. Advantages of SOS MESFETs associated with nonlinear signal processing include lower power consumption and higher operating speeds compared to similar geometry MOSFETs carrying the same current. SOS MESFET-based analog image recognition systems were fabricated and the transient response is characterized in both simulation using a TOM3 SPICE model extracted from SOS MESFETs and in experiment using image testing lab equipment. Settling times of 3.5 and 6.5 μs for one-by-four and one-by-eight arrays, respectively, were achieved with line recognition template. The corresponding power consumption for the two arrays was 9.6 and 19.2 mW, respectively.

Compact Modeling for Submicron Fully Depleted SOI MOSFET's

In this paper, we have developed a novel compact charge-conservative model for fully depleted silicon-on- -insulator MOSFETs and implemented it in SPICE3. Our model is valid for the DC, small-signal and large-signal simulations over a wide range of temperature. Simulations made using the model, following parameter extraction, are validated by comparison with experimental data. near subthreshold slope, increased saturation current and re- duced parasitic capacitances. Moreover, SOI MOSFETs are suitable in high temperature applications since they present a low leakage current and a reduced soft error ef- fect (1). Hence the availability of accurate fully depleted (FD) SOI MOSFET device model is suitable to both dig- ital and analog circuit simulation for the emerging SOI technology. To address this need, we propose in this paper a com- pact model for FD SOI MOSFETs in strong inversion. In this model, a linear relationship between the surface potential and the inversion charge density is used. The drain current and the total charges are written in terms of the inversion charge densities at the drain and source ends of the channel. The explicit unified expression of the inversion charge density is applied in these equa- tions (2, 3). Therefore, this model can be used to cal- culate the drain current and all large and small signal parameters since it includes threshold voltage roll-o, parasitic source/drain resistance eect, mobility reduc- tion due to the vertical field, carrier velocity saturation

A Unified Analytical One-Dimensional Surface Potential Model for Partially Depleted (PD) and Fully Depleted (FD) SOI MOSFETs

In this work, we present a unified analytical surface potential model, valid for both PD and FD SOI MOSFETs. Our model is based on a simplified one dimensional and purely analytical approach, and builds upon an existing model, proposed by Yu et al. [4], which is one of the most recent compact analytical surface potential models for SOI MOSFETs available in the literature, to improve its accuracy and remove its inconsistencies, thereby adding to its robustness. The model given by Yu et al. [4] fails entirely in modeling the variation of the front surface potential with respect to the changes in the substrate voltage, which has been corrected in our modified model. Also, [4] produces self-inconsistent results due to misinterpretation of the operating mode of an SOI device. The source of this error has been traced in our work and a criterion has been postulated so as to avoid any such error in future. Additionally, a completely new expression relating the front and back surface potentials of an FD SOI film has been proposed in our model, which unlike other models in the literature, takes into account for the first time in analytical one dimensional modeling of SOI MOSFETs, the contribution of the increasing inversion charge concentration in the silicon film, with increasing gate voltage, in the strong inversion region. With this refinement, the maximum percent error of our model in the prediction of the back surface potential of the SOI film amounts to only 3.8% as compared to an error of about 10% produced by the model of Yu et al. [4], both with respect to MEDICI simulation results.

Fully depleted double-gate MSDRAM cell with additional nonvolatile functionality

We demonstrate a new fully depleted (FD) double-gate (DG) MSDRAM cell, which features SONOS type storage node at the back-gate (control-gate). This single-transistor cell, based on the meta-stable dip (MSD) hysteresis effect, can also be operated in non-volatile memory (NVM) mode. The NVM functionality is achieved by Fowler–Nordheim tunneling hole injection into the nitride storage node; the injected holes induce a permanent inversion layer in silicon body. The proposed device shows a large current ratio between ‘1’ and ‘0’ states (∼10 3) and a wide memory window (∼3 V). The effect of the NVM functionality on the MSD hysteresis was investigated and combined with the effect of the control-gate bias. The SONOS charging can be used for replacing the second gate (i.e. enabling single-gate MSDRAM) or for achieving ‘unified’ memory operation.

Effects of High–Energy Neutrons on Advanced SOI MOSFETs

This work discusses the degradations caused by high-energy neutrons in advanced MOSFETs and compares them with damages created by γ-rays reviewing the original researches performed in our laboratory during last years [1-6]. Fully–depleted (FD) Silicon-on-Insulator (SOI) MOSFETs and Multiple-Gate (MuG) FETs with different geometries (notably gate lengths down to 50 nm) have been considered. The impact of radiation on device behavior has been addressed through the variation of threshold voltage (VT), subthreshold slope (S), transconductance maximum (Gmmax) and drain-induced barrier lowering (DIBL). First, it is shown that degradations caused by high-energy neutrons in FD SOI and MuG MOSFETs are largely similar to that caused by γ-rays with similar doses [1,3]. Second, it is revealed that, contrarily to their generally-believed immunity to irradiation [7, 8], very short-channel MuGFETs with thin gate oxide can become extremely sensitive to the total dose effect [2,3]. The possible reason is proposed. Third, a comparative investigation of high-energy neutrons effects on strained and non-strained devices demonstrates a clear difference in their response to high-energy neutrons exposure [6]. Finally, based on simulations and modeling of partially –depleted (PD) SOI CMOS D Flip-Flop, we show how radiation-induced oxide charge and interface states build-up can affect well-known tolerance of SOI devices to transient effects [4,5].

Two-Dimensional Analytical Model for Deriving the Threshold Voltage of a Short Channel Fully Depleted Cylindrical/Surrounding Gate MOSFET

A two-dimensional analytical model for deriving the threshold voltage of a short channel fully depleted (FD) cylindrical/surrounding gate MOSFET (CGT/SGT) is suggested. By taking into account the lateral variation of the surface potential, introducing the natural length expression, and using the Bessel functions of the first and the second kinds of order zero, we can derive potentials in the gate oxide layer and the silicon core fully two-dimensionally. Making use of these potentials, the minimum surface potential can be obtained to derive the threshold voltage as a closed-form expression in terms of various device parameters and applied voltages. Obtained results can be used to explain the drain-induced threshold voltage roll-off of a CGT/SGT in a unified manner.

Gate-induced drain leakage in FD-SOI devices: What the TFET teaches us about the MOSFET

This paper compares the gate-induced drain leakage (GIDL) in fully-depleted (FD) silicon-on-insulator (SOI) tunneling field effect transistor (TFET) and in standard metal-oxide-semiconductor FET (MOSFET) fabricated in the same process. The measurements show that the MOSFET GIDL current is lower than the GIDL in a TFET with the same junction doping, especially for devices with thick gate oxide and under low drain bias. A model describing lateral band-to-band tunneling (BTBT) is developed for GIDL in the FD-SOI TFET. By combining the model of gate-controllable tunneling diode in series with a field effect diode, we achieve an accurate picture of GIDL in FD-SOI MOSFETs.

Performance Evaluation of FD-SOI MOSFETS for Different Metal Gate Work Function

Fully depleted (FD) Silicon on Insulator (SOI) metal oxide Field Effect Transistor (MOSFET) Is the Leading Contender for Sun 65nm Regime. This paper presents a study of effects of work functions of metal gate on the performance of FD-SOI MOSFET. Sentaurus TCAD simulation tool is used to investigate the effect of work function of gates ont he performance FDSOI MOSFET. Specific channel length of the device that had been concentrated is 25nm. From simulation we observed that by changing the work function of the metal gates of FD-SOI MOSFET we can change the threshold voltage. Hence by using this technique we can set the appropriate threshold voltage of FD-SOI MOSFET at same voltage and we can decrease the leakage current, gate tunneling current and short channel effects and increase drive current.

Detailed investigation of effective field, hole mobility and scattering mechanisms in GeOI and Ge pMOSFETs

We present a methodology for accurate calculation of effective electric field in Ge and GeOI (Germanium-on-Insulator) pMOSFETs, based on the experimental determination of the parameter η, linking the inversion charge and the effective field. The fabrication procedure of wafers and devices is described. The novel extraction methodology for η factor has been validated experimentally for both bulk-Ge and fully-depleted (FD) GeOI MOSFETs. A difference in η of 20% has been found between the two structures. This correction has a significant impact on effective mobility analysis for advanced GeOI-based pMOSFETs. Furthermore, the influence of the temperature on η parameter has been investigated. The analysis reveals the behavior of the surface roughness limited mobility, which appears to be independent on T and to vary as a function of E eff - 1 for holes in Ge. An appropriate Coulomb limited mobility modelling is finally proposed, providing relevant information on the interface trap charge in undoped GeOI pMOSFET devices.

Influence of Si nanocrystal embedded in BOX on radiation and electrical properties of SOI wafer

The radiation and electrical properties of Fully-Depleted (FD) SOI wafers hardened through the implantation of Si ions were provided in this study. The results showed that the Si nanocrystal created through ion implantation could significantly improve the anti-radiation ability of FD SOI wafers by generating electron traps deep within the BOX. The existence of Si nanocrystal was confirmed by the HRTEM and XRD measurements, and the average size of Si nanocrystal was determined. Besides, the adverse effects induced by Si nanocrystal were investigated.

Impact of (Quasi-)Ballistic Transport on Operation of Complementary Metal–Oxide–Semiconductor Inverters Based on Fully-Depleted Silicon-on-Insulator and Nanowire Devices

We have developed a numerical simulation methodology to analyze the impact of both device architecture and transport properties on static circuit performance. Firstly, to simulate ballistic transport, we have enhanced the pioneering approach of quasi-ballistic mobility proposed by Rhew and Lundstrom and introduced it into a technology computer aided design (TCAD) simulator. Secondly, we have introduced the remote Coulomb scattering (RCS) limited mobility into the effective mobility and calibrated our model using experimental mobility data. We have used our approach to simulate two ultimate architectures: fully-depleted (FD) silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistor (MOSFET) (with either thin or thick buried oxide) and nanowire MOSFET. Finally, we have analyzed the impact of both transport properties and electrostatic control on the noise margin (NM) of complementary metal–oxide–semiconductor (CMOS) inverter.

Electrical Characterization of TbScO3/TiN Gate Stacks of MOS Capacitors and MOSFETs on Strained and Unstrained SOI

We investigated the electrical and structural properties of TbScO3 as an alternative gate dielectric. Rutherford backscattering spectrometry revealed a stoichiometric film while X-ray photo-electron spectroscopy indicated silicate formation at the interface. Capacitance-Voltage measurements resulted in well behaving C-V curves with no hysteresis and a low density of interface trap states in the range of 4x1011 (eVcm2)-1. Fully depleted (FD) SOI and sSOI MOSFETs fabricated with a full replacement gate process show a steep subthreshold slope down to 81 mV/dec and high Ion/Ioff ratios up to 108. Low field electron mobilities of 181 cm2/Vsec for SOI and 350 cm2/Vsec for sSOI, were extracted, which are comparable to MOSFETs with Hf based oxides. Gate induced drain leakage (GIDL) investigations indicate a trap assisted band to band tunneling.

Analysis of the Low-Frequency Noise in Graded-Channel and Standard SOI nMOSFET

In this paper a comparison between the low-frequency noise in graded-channel SOI nMOSFETs (GC SOI MOSFET) and standard fully depleted (FD) SOI nMOSFETs will be presented. The evolution of noise with bias and frequency, mainly in the GC SOI MOSFETs, will be demonstrated. Numerical bidimensional simulations are used to reproduce the same tendencies observed experimentally in order to allow for a physical insight on the noise in GC SOI transistors.

Readout ASIC With SOI Technology for X-Ray CCDs

We developed an analog front-end application specific integrated circuit (ASIC) with a fully depleted (FD) silicon-on-insulator (SOI) technology for readout of X-ray CCDs. The ASIC contains seven readout channels, each of which is equipped with the correlated double sampling circuit followed by an amplitude-to-pulse width conversion circuit. We combined the ASIC with an X-ray CCD for performance evaluation tests. We succeeded in processing analog signals from the CCD and confirmed an X-ray imaging and photon-counting capabilities by irradiating a radioisotope <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">55</sup> Fe. The energy resolution is 305 eV at 5.9 keV (full-width at half maximum) and the readout noise is 53.7 μV for power consumption of 33 mW per chip. The ASIC proves that the FD-SOI process can be a practically usable option for front-end applications.

Dynamic body potential variation in FD SOI MOSFETs operated in deep non-equilibrium regime: Model and applications

Even in fully-depleted (FD) SOI MOSFETs, the floating-body potential variations may lead to strong transient effects on the current characteristics. A physics-based model, enabling the fast computing of the potential variation with time, is proposed in this paper. The model is validated, for a wide range of technological parameters and biases, by 2D numerical simulations. This model reproduces the experimental data and clarifies the physics mechanisms responsible for the transient variations of gate and drain currents. Relevant applications in the field of EEPROM and capacitorless floating-body DRAM memories are addressed.

Self-Heating Effects in Nanoscale FD SOI Devices: The Role of the Substrate, Boundary Conditions at Various Interfaces, and the Dielectric Material Type for the BOX

In this paper, we continue our investigations on self-heating effects in nanoscale fully depleted (FD) silicon-on-insulator (SOI) devices with emphasis on what is the appropriate simulation domain needed for accurate modeling. In that context, we examine the influence of the underlying substrate on the current degradation in the active channel region and what needs to be the proper boundary conditions at the source/drain and gate contacts and the artificial-side boundaries. We finally examine the self-heating effect when the BOX is made of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SiO</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , diamond, and AlN. As such, this paper helps one estimate the minimum and the maximum limits on-current degradation due to self-heating effects in FD SOI devices.