Full Gate Research Articles

Time-optimal control of collisional SWAP gates in ultracold atomic systems

We use quantum optimal control to identify fast collision-based two-qubit $\sqrt{\text{SWAP}}$ gates in ultracold atoms. We show that a significant speed up can be achieved by optimizing the full gate instead of separately optimizing the merge-wait-separate sequence of the trapping potentials. Our optimal strategy does not rely on the atoms populating the lowest eigenstates of the merged potential, and it crucially includes accumulation of quantum phases before the potentials are fully merged. Our analyses transcend the particular trapping geometry, but to compare with previous works, we present systematic results for an optical lattice and find greatly improved gate durations and fidelities.

An FPGA-Based Hardware Accelerator for CNNs Using On-Chip Memories Only: Design and Benchmarking with Intel Movidius Neural Compute Stick

During the last years, convolutional neural networks have been used for different applications, thanks to their potentiality to carry out tasks by using a reduced number of parameters when compared with other deep learning approaches. However, power consumption and memory footprint constraints, typical of on the edge and portable applications, usually collide with accuracy and latency requirements. For such reasons, commercial hardware accelerators have become popular, thanks to their architecture designed for the inference of general convolutional neural network models. Nevertheless, field-programmable gate arrays represent an interesting perspective since they offer the possibility to implement a hardware architecture tailored to a specific convolutional neural network model, with promising results in terms of latency and power consumption. In this article, we propose a full on-chip field-programmable gate array hardware accelerator for a separable convolutional neural network, which was designed for a keyword spotting application. We started from the model implemented in a previous work for the Intel Movidius Neural Compute Stick. For our goals, we appropriately quantized such a model through a bit-true simulation, and we realized a dedicated architecture exclusively using on-chip memories. A benchmark comparing the results on different field-programmable gate array families by Xilinx and Intel with the implementation on the Neural Compute Stick was realized. The analysis shows that better inference time and energy per inference results can be obtained with comparable accuracy at expenses of a higher design effort and development time through the FPGA solution.

On the origin of drain current transients and subthreshold sweep hysteresis in 4H-SiC MOSFETs

In 4H silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs), slow drain current transients and strong sweep hysteresis govern the subthreshold regime, in particular, after negative gate stress. Although these are clearly charge carrier trapping and emission phenomena, a physical model describing the effect to a full extent is missing. In this paper, we investigate a-face n-channel 4H-SiC trench MOSFETs and record drain current transients over seven decades of time for gate voltages below and above threshold. We find clear evidence that the transients result from electron capture rather than from hole emission. Thereby, the time constant for electron capture into interface or near-interfacial defects is broadly distributed and is well characterized by a lognormal distribution. Based on the findings, we propose a physical model that consistently describes the time-dependent measured data in the full gate voltage range. The resulting trap density for the investigated MOSFETs equals 4.2 × 1012 cm–2 with a median electrical capture cross section of 2.5×10−19 cm2. The distribution of capture time constants has a width of 1.6 orders of magnitude.

Modeling and Detectability of Full Open Gate Defects in FinFET Technology

FinFET technology is an attractive candidate for high-performance and power-efficient application and is currently used for several electronic products. FinFET technology incorporates new technologies in the manufacturing processes that may generate new defect topologies which need to be considered during test generation. This paper analyzes the electrical behavior of full open gate defects, i.e., a transistor gate with infinite resistance. It is shown that classical models, called single open (SO) and interconnect open (IO), that have been proposed in the past for CMOS technology are not sufficient in FinFET technology. The modern FinFET-based logic cells using multifin and multifinger design techniques give rise to new specific defect topologies called “subset full open gate defect.” The static and dynamic electrical behaviors of the two new topologies, subset SO (SOsub) and subset IO (IOsub), are analyzed, and the detectability of the defect in the context of Boolean testing and delay testing is derived. The detectability is analyzed taking into account process variation, temperature, and power supply control.

Lateral scaling and positioning effects of top-gate electrodes on single-molecule field-effect transistors

Molecular electronics aims at integrating controllable molecular devices into circuits or machines to realize certain functions. According to device configuration, molecular field-effect transistors with top-gate electrodes have great advantages for integration. Nevertheless, from technical aspects, it is difficult to control lateral scale and position of a top-gate electrode precisely. Therefore, one problem arises in how lateral scaling and positioning effects of a top-gate electrode affect device performance. To solve this problem, the electronic transport properties of single-molecule field-effect transistor configurations modulated by a series of partial-scale top-gate electrodes with different lateral scales and positions are studied by using non-equilibrium Green’s function in combination with density functional theory, and compared with those of the full gate electrode (can be considered as a bottom gate electrode). The results show that lateral scaling and positioning effects indeed have a great impact on electronic transport properties of single-molecule field-effect transistor configurations. For -saturated 1,12-dodecanedithiol devices, larger lateral scale of a partial-scale top-gate electrode obtains larger amplification coefficient (ratio of device conductances with/without a gate electrode), and even larger than that of the full gate electrode. While lateral positioning effect has little influence on this device. For -conjugated 1,3,5,7,9,11-dodehexaene-1,12-dithiol devices, performance of a partial-scale top-gate electrode mainly depends on locations of its two edges, i.e. the number of bonds that it breaks. These results will provide theoretical directions in device designing and manufacturing in the future.

Identification Determinant Variables of the Injury Severity Crashes at Road-Railway Level Crossing in Indonesia

Abstract Accident between road and railway traffic at the railway level crossings (RLCs) is a significant issue in developing countries particularly in Indonesia. The Indonesia national traffic accident data (IRSMS) recorded approximately 900 accidents at RLCs between 2013 and 2016. In this study, accessed for 154 RLCs detail accident records can be completed. The number of accidents at RLCs in Indonesia are substantial high with a ratio of accidents and fatality accidents were 40.47 accidents/1,000 RLCs and 14.96 fatalities/1,000 RLCs respectively by comparison to the international standard. This paper adopts the ordered probit model for identifying the determinant variables of the injury severity crashes at various RLCs types (i.e. active and passive) and locations (i.e. urban and rural). The findings are as follows: rain will increase the risk of fatality, Power Two Wheelers have a high risk of fatalities in urban and less risk in rural passive RLCs; Fatal accident crossing at RLCs occur in the low traffic condition and dawn period. Finally, Male drivers are more likely being killed in the vehicles-train accidents in the RLCs. The recommendations are: First, to suggest the train authority to provide full length boom gate at both sides at the active RLC to reduce the chances for motorcyclists’ violate the boom gate from the other side of roads when train passing the level crossing. Second, for all passive RLCs must be equipped with a warning siren, flashing light prior train passing, and street light for improving alertness drivers/riders during day and night as well as in peak or non-peak hours.

Area and Energy-Efficient 4-2 Compressor Design for Tree Multiplier Implementation

Redundant gates of 4-2 compressor (hereafter, it is referred as 42C) has been removed by simplification of compressor output Boolean expression, that results in power consumption minimization. Further, the proposed design is implemented in full swing gate diffusion input logic, a low-power design technique with minimum transistor count. To evaluate the performance of existing and proposed compressor designs, they are simulated using SPICE simulation at 45 nm technology model. Also, the area is calculated from their corresponding generated layouts for the same technology model. From the simulation results, it is observed that the proposed compressor has shown performance improvement in terms of power delay product by 45% than the recently reported compressor. Further, to study the performance of proposed compressor in an application environment, a 16-bit multiplier is implemented. Its simulation results confirmed that the performance improvement is consistent in the multiplier too.

Extended quantum Maxwell demon acting over macroscopic distances

A quantum Maxwell demon is a device that can lower the entropy of a quantum system by providing it with purity. The functionality of such a quantum demon is rooted in a quantum mechanical SWAP operation exchanging mixed and pure states. We describe the setup and performance of a quantum Maxwell demon that purifies an energy-isolated system from a distance. Our cQED-based design involves two transmon qubits, where the mixed-state target qubit is purified by a pure-state demon qubit connected via an off-resonant transmission line; this configuration naturally generates an iSWAP gate. Although less powerful than a full SWAP gate, we show that assuming present-day performance characteristics of a cQED implementation, such an extended quantum Maxwell demon can purify the target qubit over macroscopic distances on the order of meters and tolerates elevated temperatures of the order of a few Kelvin in the transmission line.

Suppressing the excess OFF-state current of short-channel InAs nanowire field-effect transistors by nanoscale partial-gate

The excess OFF-state current caused by band to band tunneling (BTBT) is a serious issue particularly in short-channel nanowire (NW) field-effect transistors (FETs), especially for narrow bandgap semiconductors such as InAs. Here, to clarify the components of the OFF-current and suppress the OFF-current, we for the first time fabricate and study InAs NW FETs with nanoscale partial-gate (PG). We fabricate a series of PGFETs and a normal full-gate (FG) FET on the same NW. Based on our results, the BTBT current component can reach tens of nanoamps in a typical 250 nm-channel InAs NW FGFET, and dominate the OFF-current. In contrast, there is almost no BTBT component in the PGFET, which provides a reference for other short-channel InAs NW FETs. Furthermore, the physical mechanism of the OFF-state carrier transport is discussed, and both electrons and holes currents are proven to be very important, based on our experimental results. Also, through statistic study, we find the BTBT effect can be more serious in the devices with better gate-control. Therefore, suppressing the BTBT effect is important to the future scaling-down.

(Invited) The Scaling-Down and Performance Optimization of InAs Nanowire Field Effect Transistors

The excess OFF-state current caused by band to band tunneling (BTBT) is a serious issue for short channel nanowire (NW) field-effect transistors (FETs), especially for semiconductors with narrow bandgap such as InAs. To suppress the OFF-state current and find way to improve the properties of short channel NW FETs based on semiconductors with narrow bandgap, we for the first time fabricate and study InAs NW FETs with nanoscale partial-gate (PG). While compared with full-gate (FG) FET fabricated on the same NW, PGFET shows better OFF-state characteristics. Through studying the devices with different length of PG, different measurement conditions and fabrication processes, we find the excess OFF-state leakage current is mainly induced by the BTBT caused by the high-field at the drain-end of the channel, which can be obviously suppressed by the ungated region of PGFET. Through statistic study, we find BTBT effect can be more serious in the devices with better gate-control.

The Influence of the Dam Construction on Plant Types in Shiyang River

Shiyang River Basin, as the high extent of exploitation & utilization of its resources and severe ecological & environmental issues, has always received much attention from scholars at home and abroad. The research, with reference to previous scholars’ conclusion and field survey, showed that the dam construction has resulted in the radical changes of water resource distribution as well as water resource utilization mode, which eventually had a strong effect on plant species and community change along the middle and lower reaches of the Shiyang River. The mainly result include: 1) The vegetation area, vegetation cover and biomass all decreased, plant types had changed from wet series to xeric series, Tamarix ramosissima, Kalidium foliatum and Phragmites australis etc community had gradually decreased, the vegetation with more drought tolerance had gradually occupy the dominant position, mainly includes Nitraria tangutorum, Reaumuria soongarica, Lycium ruthenicum etc, especially Nitraria tangutorum had become constructive species in most of the place in the middle and lower reaches of the Shiyang River since 1950's. 2) In the middle and lower reaches of the Shiyang River, The vegetation formed various adaptive way and xeromorphic characteristics in order to adapt the adverse environment such as the serious sand storm, the higher difference of temperature between day and night, the lower precipitation and the higher evaporation etc. The ring gate types gradually became the main types of structure of leaf in the region of relatively severe of human disturbance, the full gate types plants and normal types plants gradually increased in the region of relatively less of human disturbance, the type of structure of leaf changed from the ring gate types and normal types to irregular molding in the region of sharply decreased of groundwater. The dam construction caused reclaiming wasteland for farming on a large scale, disproportionate use of water resource, groundwater overdraft of and deterioration of water quality etc, and this eventually lead to change of areas and types of vegetation.

Performance evolution of 4-b bit MAC unit using hybrid GDI and transmission gate based adder and multiplier circuits in 180 and 90 nm technology

This paper presents the high-speed adder circuit design based on 18 transistor (18T) full swing gate diffusion input based logic gates and transmission based techniques to compute the sum and carry bits, respectively. The proposed adder logic operates at 1.8 and 1.2 V supply voltage. The 180 and 90 nm technology are used for the proposed architectures. The proposed design consists of less power delay products and reduces 28.57% as compared to conventional 16 transistor based adder cells. The proposed adder circuit increases the transistor count by a factor of 2. The performance of the proposed 1-bit adder circuit is testified to design 4-bit ripple carry, carry save and carry select adder circuits, with reduced circuit parameters in terms of power, delay and power delay products. In addition, the performance of the proposed adder circuit are checked to design Barun and Baugh Wooley multipliers. Finally, the low power and high-speed MAC unit is designed with the proposed adder, multiplier and register circuits. The proposed MAC unit achieves significant improvements in power-delay product as compared to conventional designs. The proposed adder, multiplier and MAC unit operation is performed wih the number of samples using Monte Carlo simulation tool. The performance evolution of the circuit parameters including power, delay and power-delay products are verified using the Cadence software Virtuoso software.

First-principles study of magnetic order in graphene nanoflakes as spin logic devices

Scale effect and topological frustration can form magnetic order in the finite graphene structures (graphene nanoflakes (GNFs)). In this paper, the GNFs that can generate large net electron spin or electron spin antiferromagnetic coupling between local regions of net electron spins are classified reasonably. Representative special GNF configurations are proposed to be effectively used as fundamental logic gate devices for ultra-fast high density spintronics, and theoretically investigated by the first-principles electron structure calculations based on spin-polarized density functional theory. The first-principles calculations are performed by utilizing all-electron numerical-orbital scheme in the M11-L form of meta-GGA exchange-correlation functional. The energy spectrum of singly occupied states and the isodensity surface of total spin distribution indicate evidently that spin-single-state electrons are localized on two sides of a representative double-triangle GNF and the spin polarizations of two GNF segments are in opposite directions, resulting in antiferromagnetic coupling, which is consistent with the results derived from the graph theory and Lieb theorem. The energy of antiferromagnetic spin-coupled state is 55 meV lower than that of ferromagnetic spin-coupled state, which is obviously higher than the thermodynamic threshold of the minimum energy dissipation at room temperature. The spin coupling energy of the double triangle GNF increases with the scaling of GNF dimension increasing. The magnetic coupling strength of the double triangle GNF with and without mirror symmetry approach to the maximum stable values of 50 meV and 200 meV respectively, which are remarkably higher that of quantum dots and transition metal atom systems. Due to the fact that the spin coupling strength of the GNF logic gate spin device can reach 200 meV, it can operate normally at ambient temperature with an error rate of 0.001 which can be easily improved by an error correction technique. The calculation results demonstrate that the proposed GNF logic gate can finely operate at ambient temperature with significantly low and correctable error rate. Recent experimental studies show that graphene nanodevices on a scale of only a few nanometers can be successfully fabricated by etching technique of electron beam and scanning probe. Furthermore, the properties of GNF spin logic devices are not sensitive to intrinsic defects. The triangular GNF with n carbon rings has only (n+2)2-3 carbon atoms, while it can endure n-1 internal defects, thus persisting in non-bond states and local magnetic moments. It is suggested that the full spin logic gate devices based on GNF can be realized by using the current advanced nano-processing technology.

An improved implementation of hierarchy array multiplier using CslA adder and full swing GDI logic

In this paper, an efficient implementation of a 16 bit array hierarchy multiplier using full swing Gate Diffusion Input (GDI) logic is discussed. Hierarchy multiplier is attractive because of its ability to carry the multiplication operation withi one clock cycle. The existing hierarchical multipliers occupy more area and suffer from accumulation delay of base multiplier output bits. These issues can be addressed by incorporating carry select adder based addition and the multiplier implementation using full swing GDI logic. The basic computation blocks involved in the multiplier are AND gate and carry propagate adder. They are implemented with using full swing GDI logic. Due to their reduced transistor count and less power consumption, this multiplier implementation leads to significant improvement compared with the existing implementations. The designed and existing array multipliers are simulated at 45 nm technology model and their power consumption and delay are calculated from the simulation results. It is validated that the proposed hierarchy array multiplier based on full swing GDI logic has 27% less energy consumption than the existing design. The results confirmed that implemented multiplier has shown better performance and can be used for signal and im age processing.

Stress-induced leakage current characteristics of PMOS fabricated by a new multi-deposition multi-annealing technique with full gate last process**Project supported by the National High Technology Research and Development Program of China (Grant No. 2015AA016501) and the National Natural Science Foundation of China (Grant No. 61306129).

In the process of high-k films fabrication, a novel multi deposition multi annealing (MDMA) technique is introduced to replace simple post deposition annealing. The leakage current decreases with the increase of the post deposition annealing (PDA) times. The equivalent oxide thickness (EOT) decreases when the annealing time(s) change from 1 to 2. Furthermore, the characteristics of SILC (stress-induced leakage current) for an ultra-thin SiO2/HfO2 gate dielectric stack are studied systematically. The increase of the PDA time(s) from 1 to 2 can decrease the defect and defect generation rate in the HK layer. However, increasing the PDA times to 4 and 7 may introduce too much oxygen, therefore the type of oxygen vacancy changes.

Self-guided reconstruction for time-domain fluorescence molecular lifetime tomography.

Fluorescence probes have distinct yields and lifetimes when located in different environments, which makes the reconstruction of fluorescence molecular lifetime tomography (FMLT) challenging. To enhance the reconstruction performance of time-domain (TD) FMLT with heterogeneous targets, a self-guided L 1 regularization projected steepest descent (SGL1PSD) algorithm is proposed. Different from other algorithms performed in time domain, SGL1PSD introduces a time-resolved strategy into fluorescence yield reconstruction. The algorithm consists of four steps. Step 1 reconstructs the initial yield map with full time gate strategy; steps 2–4 reconstruct the inverse lifetime map, the yield map, and the inverse lifetime map again with time-resolved strategy, respectively. The reconstruction result of each step is used as a priori for the reconstruction of the next step. Projected iterated Tikhonov regularization algorithm is adopted for the yield map reconstructions in steps 1 and 3 to provide a solution with iterative refinement and nonnegative constraint. The inverse lifetime map reconstructions in steps 2 and 4 are based on L 1 regularization projected steepest descent algorithm, which employ the L 1 regularization to reduce the ill-posedness of the high-dimensional nonlinear problem. Phantom experiments with heterogeneous targets at different edge-to-edge distances demonstrate that SG

Performance comparison of single and dual metal dielectrically modulated TFETs for the application of label free biosensor

In this work, we perform a comparative analysis between single and dual metal dielectrically modulated tunnel field-effect transistors (DMTFETs) for the application of label free biosensor. For this purpose, two different gate material with work-function as ϕM1 and ϕM2 are used in short-gate DMTFET, where ϕM1 represents the work-function of gate M1 near to the drain end, while ϕM2 denotes the work-function of gate M2 near to the source end. A nanogap cavity in the gate dielectric is formed by removing the selected portion of gate oxide for sensing the biomolecules. To investigate the sensitivity of these biosensors, dielectric constant and charge density within the cavity region are considered as governing parameters. The work-function of gate M2 is optimized and considered less than M1 to achieve abruptness at the source/channel junction, which results in better tunneling and improved ON-state current. The ATLAS device simulations show that dual metal SG-DMTFETs attains higher ON-state current and drain current sensitivity as compared to its counterpart device. Finally, a dual metal short-gate (DSG) biosensor is compared with the single metal short-gate (SG), single metal full-gate (FG), and dual metal full-gate (DFG) biosensors to analyse structurally enhanced conjugation effect on gate-channel coupling.

Energy and area efficient hierarchy multiplier architecture based on Vedic mathematics and GDI logic

Hierarchy multiplier is attractive because of its ability to carry the multiplication operation within one clock cycle. The existing hierarchical multipliers occupy more area and also results in more delay. Therefore, in this paper, a method to reduce the computation delay of hierarchy multiplier by employing CslA and Binary to Excess 1 Converter (BEC) is proposed. The use of BEC eliminates the n/4 number of adders, existing in the conventional addition scheme, where n denotes the multiplier input width. As the area of the hierarchy multiplier is determined by its base multiplier, the base multiplier is realized with the proposed Vedic multiplier, which has small area and operates with less delay than the conventional multipliers. In addition, the reduction of power consumption in the hierarchy multiplier can be ensured by implementing the designed multiplier with full swing Gate Diffusion Input (GDI) logic. The performances of the proposed and the existing multipliers are evaluated by Cadence SPICE simulator using 45nm technology model. From the simulation results, the performance parameters namely, delay and power consumption are calculated. Further, the area is measured from the corresponding layout for the same technology model. It is examined from the results that the proposed multiplier operates with 17% lesser power delay product than the recently reported hierarchy multiplier. The Monte Carlo simulation is performed to understand the robustness of the proposed hierarchy multiplier.

Titanium Silicide/Titanium Nitride Full Metal Gates for Dual-Channel Gate-First CMOS

We demonstrate a thermally stable titanium silicide/titanium nitride (TiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> /TiN) full metal gate (FMG) for dual-channel gate-first high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula> /metal gate complementary metal–oxide–semiconductor technology. Unlike prior tungsten-based FMG, the simple TiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> /TiN gate electrode does not require any additional barrier layer preventing oxygen down-diffusion during high-temperature processing, as the TiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> itself blocks oxygen. With HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based gate dielectrics and without any oxygen scavenging scheme, we thus demonstrate a capacitance-equivalent thickness in inversion ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T_{\mathrm {inv}})$ </tex-math></inline-formula> of 1.11 nm, corresponding to an equivalent oxide thickness of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 0.7$ </tex-math></inline-formula> nm. Silicon channel nFET and silicon germanium channel pFET parametrics are similar to those of control devices utilizing a conventional a-Si/TiN metal-inserted poly-Si stack (MIPS) gate, while providing superior gate sheet resistance. By supplanting MIPS with such an FMG, we anticipate that contacted gate pitch can be scaled aggressively via reduced gate height and borderless source/drain contacts.

Performance improvement in tree multiplier using full swing GDI logic based CLA adder

Designing multiplier with high speed low power and minimal layout structure is of prime importance. In this paper, we propose a new architecture of 8 × 8 Wallace tree multiplier by incorporating 4-2 compressor and full adder during the partial products reduction process. Also, the final carry propagate addition is performed by carry look ahead adder to reduce the delay. Further, the multiplier is implemented using full swing gate diffusion input (GDI) logic. This design is simulated using Cadence virtuoso at 45 nm technology model. The simulation results reveal that the proposed multiplier achieves 23% power reduction than the conventional tree multiplier. Also, a large amount of reduction in wiring head is attained for the proposed multiplier. Further, an analysis of circuit's performance variation with respect to process variations is done by Monte Carlo simulation. The results confirmed that proposed multiplier has more immune against process variation while comparing with existing designs.