Modeling and Detectability of Full Open Gate Defects in FinFET Technology

Abstract

FinFET technology is an attractive candidate for high-performance and power-efficient application and is currently used for several electronic products. FinFET technology incorporates new technologies in the manufacturing processes that may generate new defect topologies which need to be considered during test generation. This paper analyzes the electrical behavior of full open gate defects, i.e., a transistor gate with infinite resistance. It is shown that classical models, called single open (SO) and interconnect open (IO), that have been proposed in the past for CMOS technology are not sufficient in FinFET technology. The modern FinFET-based logic cells using multifin and multifinger design techniques give rise to new specific defect topologies called “subset full open gate defect.” The static and dynamic electrical behaviors of the two new topologies, subset SO (SOsub) and subset IO (IOsub), are analyzed, and the detectability of the defect in the context of Boolean testing and delay testing is derived. The detectability is analyzed taking into account process variation, temperature, and power supply control.