A New Defect Model due to a Dust Particle Affecting the Fingers of FinFET Logic Gates

Abstract

The continuous scaling in semiconductor technolo- gies has allowed faster devices with lower power consumption. FinFET technology has become an attractive candidate for high-performance and power-efficient applications. This paper proposes a new defect model that could occur in FinFET technology using Self-Aligned Double Patterning (SADP) and replacement metal gate (RMG) process. This new defect was found by analyzing the impact of a single dust particle in the manufacturing process flux. A single dust particle disconnects two gate transistors from their inputs, and both the two disconnected inputs and the two disconnected gates have a zero-resistance bridge defect. The logic and delay behavior of the defect are analyzed using SPICE electrical simulator. A unique behavior is observed for the defect, whose detection can be missed by existing test generation methodologies. The test pattern conditions to detect the defect using boolean and delay test techniques are determined, showing that the defect requires specific test generation.