Full Gate Research Articles

Numerical investigation of heat transfer characteristics for Subsea Xmas tree assembly

This study focuses on the heat transfer characteristic of a horizontal subsea Xmas tree assembly at a high spatial resolution. Computational fluid dynamics (steady Reynolds-averaged Navier-Stokes) in combination with Low Reynolds number modelling (LRNM) is adopted for heat transfer analysis, which has been validated against a full scale underwater gate valve heat transfer experiment with good agreements. The characteristics of cold sea water flowing through the subsea tree, and of convection heat transfer between the subsea tree and ambient cold water are obtained. The typical “hot spots,” which have high Convection heat transfer coefficient (CHTC) and create great large amounts of heat loss, are numerically determined. Under the designed water depth, the effects of installation orientation, sea water velocity, and inner oil temperature on convection heat transfer are investigated as well. Such work is significant for thermal design of the subsea tree to increase structural reliability and flow assurance level.

(Invited) An Investigation of the InGaAs MOS System for Future High Mobility Channel Applications

As silicon devices reach the limit of dimensional scaling there is a growing interest in the use of high electron mobility channels, such as InxGa1-xAs, in conjunction high dielectric constant (high-k) gate oxides for n-channel Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) in FinFET structures [1] and in 3D integration schemes [2]. The understanding and control of electrically active defect states at the high-k/InxGa1-xAs interface and of charges within the atomic layer deposited (ALD) high-k films will be essential for the successful implementation of high mobility channel materials in MOSFET or tunnel FET configurations. The objective of this presentation will be to provide an overview of the current understanding of the density and distribution of electrically active defects at the high-k/InGaAs interface and of defect states located in the interfacial oxide transition region which are manifest as accumulation frequency dispersion and capacitance-voltage hysteresis. The presentation will focus on InGaAs with a 53% Indium concentration. The electrically active interface state density distribution is determined from fully fabricated InGaAs MOSFET structures based on the full gate capacitance in conjunction with the Maserjian Y-function and Poisson-Schrodinger simulations [3]. Comparisons to simulations will be discussed in terms of identifying potential candidates for the physical origin of the interface defects. Very significant progress has been made in recent years in the passivation and intrinsic elimination of high-k/In0.53Ga0.47As interface defects to the point where genuine surface inversion for n and p type InGaAs MOS structures can be achieved and this research will be reviewed [4]. The characteristic signatures of capacitance and conductance, which indicate genuine surface inversion for an InGaAs MOS structure in inversion, will also be discussed [5]. While significant attention has been focussed on interface states and fixed charges in the InGaAs MOS system, the issue capacitance-voltage (CV) hysteresis has received relatively little attention to date [4]. This is now becoming a more pressing issue as progress is being made in controlling interface defect levels. Results will be presented covering CV hysteresis for the HfO2/InGaAs and Al2O3/InGaAs MOS structures with a range of high-k oxide thicknesses. The experimental results indicate that the defect states responsible for the hysteresis are located in the oxide transition region near the InGaAs/high-k interface and that engineering of this interface region, which contains native oxides of In, Ga and As, is the key to the control of CV hysteresis and accumulation frequency dispersion [7]. Finally, the presentation will cover the application of CV analysis to the understanding and quantification of charged defect components for InGaAs on insulator structures for 3D integration [8]. The authors acknowledge the financial support of Science Foundation Ireland through the INVENT project (SFI/09/IN.1/I2633) and the EU through the project COMPOSE3 (FP7-ICT- 2013-11-619325). [1] M. Radosavljevic et al., Tech.Dig.-Int. Electron Devices Meet, 126 (2010) [2] L. Czornomaz, et al., Tech.Dig.-Int. Electron Devices Meet. 6479088, (2012) [3] V. Djara, et al., Microelectronic Engineering 109 182–188 (2013) [4] N. Goel, D. et al., Tech. Dig. - Int. Electron Devices Meet. 363, (2008) [5] É. O’Connor, et al., Appl. Phys Lett 99, 212901 (2011) [6] Scott Monaghan, et al., IEEE Transaction on Electron Devices, 61, 4176 (2014) [7] Jun Lin, et al., J. Appl. Phys. 114, 144105 (2013) [8] K. Cherkaoui et al., Microelectronic Engineering 147 63–66 (2015)

Full gate voltage range Lambert-function based methodology for FDSOI MOSFET parameter extraction

A new full gate voltage range methodology using a Lambert W function based inversion charge model, for extracting the electrical parameters in FDSOI nano-MOSFET devices, has been developed. Split capacitance–voltage measurements carried out on 14nm technology FDSOI devices show that the inversion charge variation with gate voltage can be well described by a Lambert W function. Based on the drain current equation in the linear region including the inversion charge described by the Lambert function of gate voltage and the standard mobility equation enables five electrical MOSFET parameters to be extracted from experimental Id–Vg measurements (ideality factor, threshold voltage, low field mobility, first and second order mobility attenuation factors). The extracted parameters were compared with those extracted by the well-known Y-function in strong inversion region. The present methodology for extracting the electrical MOSFET parameters was verified over a wide range of channel lengths on nano-scale FDSOI devices, demonstrating its simplicity, accuracy and robustness.

Design of Logic Circuits Using Reversible Gates

Reversible logic has become one in all the promising analysis directions in low power dissipating circuit style within the past few years and has found its applications in low power CMOS style, cryptography, digital signal process, optical scientific discipline and engineering. This paper presents a quantum price economical reversible full adder gate and Reversible Decoder in engineering. This gate will work on an individual basis as a reversible full adder & Decoder unit and needs just one clock cycle. The planned gate may be a universal gate within the sense that it may be wont to synthesize any whimsical mathematician functions. To implement reversible logic gates we tend to are planning Full adder and Decoder circuit by mistreatment the T-Spice simulation and calculate the ability consumption with TSMC018 nm Technology

Characterization of Epitaxial Si:C:P and Si:P Layers for Source/Drain Formation in Advanced Bulk FinFETs

Since quite a few years, source/drain strain engineering has been widely adopted in the manufacturing of integrated circuits to increase the carrier mobility and drive current of Si MOSFETs [1-3]. Even for sub 20nm bulk-FinFET devices, the source/drain epitaxy is expected to remain an effective and essential ingredient for device performance improvement [4,5]. In this work, we present the characterization of epitaxial in-situ phosphorus doped silicon and silicon carbon films (Si:P/Si:C:P) and discuss their integration in a raised and recessed bulk-fin geometry. The Si:C:P layers have been deposited using a low temperature selective Cyclic Deposition and Etch (CDE) process [6,7] while the Si:P films were grown using both cyclic and non-cyclic selective processes. All depositions were done in a 300 mm ASM Intrepid XPTM reduced-pressure chemical vapor deposition system (RPCVD) using traditional deposition and etch precursors. For the CDE processes discussed in this work, typical phosphorus concentrations of ~3e20 at/cm3 were obtained for carbon contents ranging from 0 to 2%. Fig.1 shows the resistivity of such layers versus total carbon content derived from micro-Hall and Secondary Ion Mass Spectrometry (SIMS) measurements on (80µm)2 pads. Introducing more carbon in the layers leads to an expected increase in resistivity due to a loss in substitutional phosphorus [8]. For the wafers with full gate and spacers, the epi was grown on underlying activated extensions without recess. Also shown is the resistivity decrease by use of bilayers with equal Si:C:P/Si:P thicknesses. For the non-CDE Si:P processes, phosphorus contents as high as 10% could be achieved which introduce tensile strain without the presence of carbon [9]. To be compatible with scaled fin dimensions, the in-situ H2 bake conditions were optimized to minimize the Si reflow and still preserve a sufficiently large oxide removal efficiency in combination with the pre-epi HF dip. Examples of reflow during H2 bake are shown in Fig.2.The selectivity of the epi processes was tuned by varying the amount of etching per cycle by either changing the etch process parameters or the etch time per cycle. Increasing the etching per cycle makes the process selective towards the oxide and nitride layers used in the integrated devices and also decreases the side-wall roughness along the fins. An optimum has to be found as the increased etching also lowers the carbon content and reduces the process throughput. Finally, we also report on the use of post-epi millisecond laser anneal which turns out to be a useful integration knob to lower the post epi resistivity while still preserving the strain. The largest improvements can be observed for strained Si:P layers with high phosphorus incorporation. From Hall and SIMS measurements on blanket and patterned wafers it can be derived that the dopant activation is strongly increased (in some cases up to 300%) resulting in a ~50% reduction of the resistivity which makes this process an attractive alternative to conventional carbon doped layers (example see Fig.3). Acknowledgements The imec core CMOS program members, European commission, local authorities and imec pilot line are acknowledged for their support.

(Invited) Gate Stacks for Silicon, Silicon Germanium, and III-V Channel MOSFETs

High-k gate dielectrics such as HfO2 and metal gate electrodes such as TiN have been deployed across a wide range of CMOS logic products in both the low-power (e.g., mobile) and the high-performance (e.g., server) space. Available device geometries include planar field-effect transistors on bulk Si, on partially depleted silicon-on-insulator (PDSOI), and on fully depleted SOI (FDSOI), as well as FinFETs. During the decade-long effort leading up to successful high-k/metal gate (HKMG) implementation, much has been learnt about the fundamental materials science underlying such gate stacks. Yet, research continues in order to ensure continued circuit density and performance scaling.After reviewing the gate-first and gate-last (or replacement gate) approaches to HKMG implementation, I will discuss device challenges that can be resolved by materials engineering on the atomic scale. A prime example is the threshold voltage (Vt) challenge, which is caused by charged oxygen vacancies in hafnium-based gate dielectrics formed at elevated temperatures, thus increasing pFET Vt. These vacancies can be filled by lateral or top-down oxidation. As an alternative, additional Vt-setting techniques can be employed, such as metal oxide capping layers (e.g., Al2O3 or La2O3 for pFET and nFET, respectively) that form permanent electrical dipoles, or SiGe channels (cSiGe) which modulate the band offsets while additionally providing a welcome hole mobility boost. A second example is continued equivalent oxide thickness (EOT) scaling. We have developed the approach of metal-gate-induced remote oxygen scavenging, which results in a thinning of the SiO2 layer at the high-k/channel interface. In this way, EOT of 0.4-0.5 nm can be reached for both nFET and pFET. I will in particular discuss our recent results on aggressive cSiGe pFET scaling (Fig. 1), including the dependence of hole mobility (Fig. 2) and of negative bias temperature instability (NBTI) reliability on EOT and thus on interfacial SiO2thickness [1].In the second part of my talk, I will show that HKMG not only provides the well-known gate-length scaling benefit through improved electrostatics, but it can also directly enable aggressive device pitch and density scaling through borderless (semi-self-aligned) source-drain (S/D) contacts [2]. Conventional gate-first high-k/metal gate (HKMG) CMOS technologies employ metal-inserted poly-Si stacks (MIPS) such as a-Si/TiN, where the amorphous Si serves as a precursor for low-sheet-resistance (Rs) self-aligned NiSi on the gates and as an oxygen barrier preventing high-k/Si interfacial SiO2 growth. A full metal gate (FMG, Fig. 3), instead containing a deposited low-Rs metal layer, can be encapsulated in a dielectric resistant to the S/D contact etch, resulting in borderless contacts. We have developed two FMG electrodes based on TiSix/TiN and W/TaMN/TiN (M = oxygen scavenging metal). With both FMG on Hf-based gate dielectrics, Si channel nFET and SiGe channel pFET parametrics and reliability similar to those of poly-Si/TiN control devices are achieved, with good EOT scalability [3,4].Finally, I will provide an outlook on high-k gate dielectrics for high-mobility III-V channel materials. Specifically, I will compare three interface approaches to InGaAs channel nFET gate stack formation. The first is based on direct high-k deposition onto InGaAs, while the other two approaches rely on the insertion of an amorphous Si or an epitaxial InP capping layer to passivate the InGaAs. The impact of such caps on interface trap density and scalability will be discussed.[1] M.M. Frank et al., ECS Solid State Lett. 2, N8 (2013).[2] S.-C. Seo, et al., VLSI, p. 36 (2011).[3] M. M. Frank et al., as discussed at SISC 2011.[4] M. M. Frank et al., as discussed at SISC 2013..

A Novel Structure Trench IGBT with Full Hole-Barrier Layer

A Full Hole-barrier Trench gate Insulated Gate Bipolar Transistor (FH-TIGBT) device structure is proposed for the first time. Compared with Carrier Stored Trench IGBT (CSTBT), which adds a carrier stored n layer between p base and n base in Trench IGBT (TIGBT), the new structure appends an n region located in the bottom of the trench gate. The result of Process and device simulations shows that the proposed device has lowered saturation voltage and larger capability of carrying current compared to either conventional trench IGBT or CSTBT. And the characteristics of turn-off time and breakdown voltage have negligibly changed. Further more, it has strongly positive temperature coefficient of on-state voltage, which means paralleling is very simple for the new device.

Electrolyte gate dependent high-frequency measurement of graphene field-effect transistor for sensing applications

We performed radiofrequency (RF) reflectometry measurements at 2–4 GHz on electrolyte-gated graphene field-effect transistors, utilizing a tunable stub-matching circuit for impedance matching. We demonstrate that the gate voltage dependent RF resistivity of graphene can be deduced, even in the presence of the electrolyte which is in direct contact with the graphene layer. The RF resistivity is found to be consistent with its DC counterpart in the full gate voltage range. Furthermore, in order to access the potential of high-frequency sensing for applications, we demonstrate time-dependent gating in solution with nanosecond time resolution.

A Novel Design of Reversible Multiplier Circuit

Adders and multipliers are two main parts of arithmetic units of computer hardware and play important role in reversible computations. This paper introduces a novel reversible 4×4 multiplier circuit that is based on an advanced “Partial Product Generation Circuits” (PPGC) with Peres gates only without duplicating gates. Again, an optimized Peres full adder reversible gate is used in “Reversible Parallel Adder” (RPA) part with accompaniment with the carry save adder technique. Comparison of the proposed design with previous ones shows that the proposed reversible multiplier improves the quantum parameters. The proposed design shows lower quantum cost and depth with the help of a novel design in PPGC. The circuit cost of the proposed design is a little higher than the best compared design, but the proposed design shows the lowest total cost which is defined as sum of quantum cost and circuit cost. Moreover, the number of gates, garbage input and output has no change regarding to the best compared design. The proposed multiplier can be generalized as an n×n bit multiplication.

A novel 4H–SiC MESFET with recessed gate and channel

New structures named as recessed gate and channel (RGC) silicon carbide (SiC) based metal semiconductor field effect transistors (MESFETs) are reported in this paper, in which the gate is recessed into the channel, and the channel is recessed into the p-buffer layer at the source and/or the drain side. Important parameters such as short channel effect, maximum DC trans-conductance (gm), drain current, breakdown voltage and output resistance of the proposed structures are simulated and compared with the conventional 4H–SiC MESFET. Simulation results disclose that, compared to the conventional structure, the structure with recessed full gate and channel (FGC):1.Improves the DC trans-conductance (gm).2.Increases the output resistance.3.Enhances the breakdown voltage.4.Reduces the short channel effect.Moreover, source side recessed gate and drain side recessed channel (SG–DC) structure has higher gm and output resistance in comparison with the conventional structure. Drain side recessed gate and source side recessed channel (DG–SC) structure has larger breakdown voltage and drain current than those of the conventional structure.

Monolithic integration of light-emitting diodes and power metal-oxide-semiconductor channel high-electron-mobility transistors for light-emitting power integrated circuits in GaN on sapphire substrate

We report the demonstration of monolithically integrated light-emitting diodes (LEDs) and power metal-oxide-semiconductor channel high-electron-mobility transistors (HEMTs) in GaN. The structure comprised a direct epitaxial integration of layers typical for a GaN-based LED grown directly on top of the layers of a GaN-based HEMT. The layers were then fabricated into a serially connected pair of GaN LED and metal-oxide-semiconductor-gated 0.3 μm-channel HEMT by exposing the LED/HEMT epitaxial layers in selective area etching. The resulting monolithically integrated circuit shows a full gate voltage modulation of the light output power. This demonstrates compatibility of group-III nitride LED and HEMT processes.

Electrically active interface defects in the In0.53Ga0.47As MOS system

• The energy distribution of electrically active interface states at the Al 2 O 3 /In 0.53 Ga 0.47 As interface has been evaluated. • Analysis reveals a peak of donor-like interface trap density 1.5 × 10 13 cm −2 eV −1 located at ∼0.36 eV above E v . • Acceptor-like interface traps are also present located in the In 0.53 Ga 0.47 As conduction band . • The interface state distribution is similar to reports for others oxides. • Results suggest the interface states originate from the In 0.53 Ga 0.47 As surface. In this work we present experimental results examining the energy distribution of the relatively high (>1 × 10 12 cm −2 eV −1 ) density of electrically active defects which are commonly reported at the interface between high dielectric constant (high- k ) thin films and In 0.53 Ga 0.47 As. The interface state distribution is examined for the Al 2 O 3 /In 0.53 Ga 0.47 As metal-oxide-semiconductor (MOS) system based on analysis of the full gate capacitance ( C g – V g ) of the surface n -channel In 0.53 Ga 0.47 As MOS transistors. The experimental capacitance, recorded at −50 °C and 1 MHz to approximate a high frequency response, is compared to the theoretical C g – V g response to evaluate the interface state distribution across the In 0.53 Ga 0.47 As energy gap and extending into the In 0.53 Ga 0.47 As conduction band. To improve the accuracy of the fitting process, the Maserjian Y-function was used in the modeling of the interface defects and fixed oxide charge densities. The analysis reveals a peak of donor-like interface traps with a density of 1.5 × 10 13 cm −2 eV −1 located at ∼0.36 eV above the In 0.53 Ga 0.47 As valence band edge, a high density of donor-like states increasing towards the In 0.53 Ga 0.47 As valence band. The analysis also indicates acceptor-like interface traps located in the In 0.53 Ga 0.47 As conduction band, with a density of ∼2.5 × 10 13 cm −2 eV −1 at 0.3 eV above the In 0.53 Ga 0.47 As conduction band minima. The reported interface state density is similar to reports for others oxides, suggesting that the recorded interface states originate from the In 0.53 Ga 0.47 As surface.

Charge Pumping Measurements of Radiation-Induced Interface-Trap Density in Floating-Body SOI FinFETs

We demonstrate that, by monitoring source and drain currents during alternating-current gate pulses, reliable estimates of radiation-induced interface-trap density can be obtained for conventional floating-body SOI FinFETs without body contacts. Estimates of effective interface-trap densities are shown for two development stage technologies, before irradiation, and for doses up to 1 Mrad(SiO2). Straightforward estimates of effective interface-trap density are obtained for these floating-body FinFETs, with either a high-K or oxynitride gate dielectric, when the fin width is less than ~70 nm, the channel length is less than ~100 nm, and there is full gate control of the relevant interfaces. This modified charge pumping technique provides estimates of interface-trap density without detailed analysis, adjustable fitting parameters, and/or device simulation, in contrast to DCIV and/or gated-diode techniques. Moreover, this technique enables more accurate estimates of radiation-induced interface-trap density in floating-body FinFETs than midgap charge separation in cases for which isolation leakage contributes significantly to subthreshold current-voltage stretchout.

Rare-Earth Scandate/TiN Gate Stacks in SOI MOSFETs Fabricated With a Full Replacement Gate Process

Terbium scandate (TbScO3) and lanthanum scan date (LaScO3) have been investigated as gate dielectrics for metal-oxide-semiconductor field-effect transistors on both silicon-on-insulator (SOI) and strained SOI (sSOI) substrates. X-ray photoelectron spectroscopy analysis revealed the presence of a silicate at the interface for TbScO3 on Si, whereas a silicate/SiO2-like interface was found for the LaScO3 on Si. A full replacement gate process was developed to fabricate high-κ/metal gate fully depleted transistors on SOI and sSOI. LaScO3 transistors with a gate length of 2 μm show excellent characteristics with steep subthreshold slopes of 72 mV/dec, high Ion/Ioff ratios, and electron mobility of 180 cm2/V · s for SOI and 375 cm2/V · s for sSOI at low field, which is superior to corresponding TbScO3 de vices. All sSOI transistors showed 2 times higher electron mobility than SOI reference devices.

Integration of $\hbox{LaLuO}_{3} \ (\kappa \sim \hbox{30})$ as High-$\kappa$ Dielectric on Strained and Unstrained SOI MOSFETs With a Replacement Gate Process

The integration of lanthanum lutetium oxide (LaLuO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) with a n value of 30 is, for the first time, demonstrated on strained and unstrained SOI n/p-MOSFETs as a gate dielectric with a full replacement gate process. The LaLuO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /Si interface showed a very thin silicate/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interlayer with a D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> level of 4.5 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> (eV · cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> . Fully depleted n/p-MOSFETs with LaLuO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /TiN gate stacks indicated very good performance with steep subthreshold slopes of ~70 mV/dec and high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ratios. In addition, strained SOI shows enhanced electron mobilities with a factor of 1.7 compared to SOI. Both electron and hole mobilities for LaLuO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> on SOI are similar to the mobilities in reported Hf-based high-κ devices.

Atom probe analysis of a 3D finFET with high-k metal gate

The atom probe analysis of a full gate stack (metal gate/high-k dielectric) in a 3D finFET is reported. The measurement reliability in this kind of heterogeneous structure is discussed in the light of different artefacts, i.e. mass overlap and 3D reconstruction artefacts.

Electrical Characterization of TbScO3/TiN Gate Stacks of MOS Capacitors and MOSFETs on Strained and Unstrained SOI

We investigated the electrical and structural properties of TbScO3 as an alternative gate dielectric. Rutherford backscattering spectrometry revealed a stoichiometric film while X-ray photo-electron spectroscopy indicated silicate formation at the interface. Capacitance-Voltage measurements resulted in well behaving C-V curves with no hysteresis and a low density of interface trap states in the range of 4x1011 (eVcm2)-1. Fully depleted (FD) SOI and sSOI MOSFETs fabricated with a full replacement gate process show a steep subthreshold slope down to 81 mV/dec and high Ion/Ioff ratios up to 108. Low field electron mobilities of 181 cm2/Vsec for SOI and 350 cm2/Vsec for sSOI, were extracted, which are comparable to MOSFETs with Hf based oxides. Gate induced drain leakage (GIDL) investigations indicate a trap assisted band to band tunneling.

The High-Mobility Bended n-Channel Silicon Nanowire Transistor

This work demonstrates a method for incorporating strain in silicon nanowire gate-all-around (GAA) n-MOSFETs by oxidation-induced bending of the nanowire channel and reports on the resulting improvement in device performance. The variation in strain measured during processing is discussed. The strain profile in silicon nanowires is evaluated by Raman spectroscopy both before device gate stack fabrication (tensile strains of up to 2.5% are measured) and by measurement through the polysilicon gate on completed electrically characterized devices. Drain current boosting in bended n-channels is investigated as a function of the transistor operation regime, and it is shown that the enhancement depends on the effective electrical field. The maximum observed electron mobility enhancement is on the order of 100% for a gate bias near the threshold voltage. Measurements of stress through the full gate stack and experimental device characteristics of the same transistor reveal a stress of 600 MPa and corresponding improvements of the normalized drain current, normalized transconductance, and low-field mobility by 34% (at maximum gate overdrive), 50% (at g max), and 53%, respectively, compared with a reference nonstrained device at room temperature. Finally, it is found that, at low temperatures, the low-field mobility is much higher in bended devices, compared with nonbended devices.

Dopant enhanced in nickel silicide formation for high-k dielectric applications

The thermal stability of fully silicided NiSi with arsenic doping on silicon was investigated. The combination of full nickel silicidation gate electrodes and hafnium based high-k gate dielectrics is one of the most promising gate stacks to replace poly-Si/SiO2/Si gate stacks in the future complementary metal–oxide–semiconductor (CMOS) sub-45 nm technology node. The aims of the work were to investigate the Ni silicide phase-related issues associated with arsenic dopant and thermal annealing on Ni–FUSI/HfO2/Si and Ni–FUSI/HfSiO/Si gate stacks. It was found that arsenic-incorporation demonstrated some improvement in both morphology and phase stability of nickel silicided films at high processing temperatures regardless underlying gate dielectrics. The correlations of Ni–Si phase transformation and arsenic doapnt with their electrical and physical changes were established by sheet resistance measurements, X-ray diffraction (XRD), atomic force microscopy (AFM), and X-ray photoelectron spectroscopy (XPS) analysis. Furthermore, the modulation of the work function (WF) of Ni fully silicided gates by arsenic impurity is presented, comparing the effects of dopant (As) on the WF and silicide phases (NiSi and NiSi2). It confirmed that the work function of NiSi can be tuned by implanting arsenic dopant, but it ineffective for NiSi2 phase.

LCD 생산공정의 전게이트 시각 검사를 위한 공정 제어장치 개발

본 연구개발에서는 정해진 환경에서 최대의 불량검출 능력을 발휘할 수 있도록 공정을 개선하기 위하여 전게이트 시각검사에 필수적인 FGV 패턴발생 장치와 공정제어 장치를 개발하였다. 본 연구개발을 통하여 접촉손실(Tact Loss)을 0에 근접 한 수준으로 유지할 뿐만 아니라 손실 및 에러 발생시 신속한 대처가 가능하여 모듈의 수율을 향상시킬 수 있을 것으로 기대된다. 또한 세부 동작 시퀀스를 제어하기 위한 H/W와 S/W 시스템을 생산라인에 실장하고 성능점검 및 인증을 수행한 결과 Tact에 의한 Pixel 불량의 경우는 98.1%, Line 불량의 경우는 99.1%의 검출율을 나타내었으며, Gate 및 Visual 레벨 테스트를 포함한 모듈공정 전체의 수율이 98.3%까지 증가하였다. This research developed process control device and FGV pattern generating device essential for full gate visual inspection to improve process so that defect detection capability may be maximized in specified environment. The devices developed in this research, which can be swiftly replaced in case loss or error occurs, are anticipated to improve module yield as well as maintain tact loss near '0'. In addition, as a result of mounting H/W and S/W system to control detailed operation sequence in production line and executing performance check and verification, detection rates were 98.1% and 99.1% respectively for pixel defect by tact and line defect, and yield of the entire module process including gate and visual level test increased up to 98.3%.