Front End Of Line Research Articles

High-Data-Rate Modulators Based on Graphene Transistors: Device Circuit Co-Design Proposals

The multifunctionality feature of graphene field-effect transistors (GFETs) is exploited here to design circuit building blocks of high-data-rate modulators by using a physics-based compact model. Educated device performance projections are obtained with the experimentally calibrated model and used to choose an appropriate improved feasible GFET for these applications. Phase-shift and frequency-shift keying (PSK and FSK) modulation schemes are obtained with 0.6 GHz GFET-based multifunctional circuits used alternatively in different operation modes: inverting and in-phase amplification and frequency multiplication. An adequate baseband signal applied to the transistors’ input also serves to enhance the device and circuit performance reproducibility since the impact of traps is diminished. Quadrature PSK is also achieved by combining two GFET-based multifunctional circuits. This device circuit co-design proposal intends to boost the heterogeneous implementation of graphene devices with incumbent technologies into a single chip: the baseband pulses can be generated with CMOS technology as a front end of line and the multifunctional GFET-based circuits as a back end of line.

Exploring thermal effects of advanced backside power delivery network beyond 3 nm node

Backside Power Delivery Networks (BSPDNs) address scaling issues by relocating power, boosting efficiency and density. However, thermal effects pose challenges. In this work, a comprehensive thermal analysis of BSPDN is performed to elaborate the key modulation factors and possible optimization approaches, where the specific backside metal layers are constructed to investigate the impacts of operating conditions, via distribution and materials on thermal effects. To improve the simulation efficiency, the effective thermal conductivity is employed to simplify the Nanosheet (NSH) FET based front-end-of-line (FEOL) and other layers at the 3 nm technology node. Results show that non-uniform via distribution in BSPDN causes temperature fluctuations, but augmenting Backside Via counts effectively mitigates local peak temperature increases from higher power. For BSPDN, backside cooling solutions outperform frontside in efficiency, particularly at high via densities. Using high thermal conductivity inter-metal dielectric (IMD) materials significantly reduces global temperature rise and fluctuations from non-uniform vias in BSPDN, enhancing PDN design flexibility.

(Invited) 2D Semiconductors from Spin-on Molecular Chemistries for Direct Large-Scale Integration

In this talk, I will discuss our recent developments centered on a process to produce fully soluble solutions from a unique molecular chemistry. This enables the creation of wafer-scale monolayers of MoS2, a prominent 2D semiconductor for logic and memory devices. This molecule can be dissolved in common solvents and spin-coated onto various substrates, including crystalline substrates, printed electrodes, and polymers. It can also be integrated into gate-all-around (GAA) 3D transistor structures for logic devices. Our method of rapidly synthesizing large-area MoS2 films, particularly in monolayer form via spin-coating, represents a novelty, as it hasn't been demonstrated previously with a single-source chemistry. This advancement is a significant step toward scalable synthesis of wafer-scale 2D semiconductor thin films, eliminating the need for post-growth wafer transfer techniques, a requirement with films grown by chemical vapor deposition (CVD) methods. Our fabrication process highlights the potential of using a single-source chemical precursor to develop monolayer 2D semiconductors that exhibit commendable transport characteristics and optical properties, which enhance with rising crystallization temperatures. Consequently, it holds promise as a semiconductor for microelectronic transistor channels in both back-end-of-line (BEOL) and front-end-of-line (FEOL) architectures.

Si/SiO2 silicon-on-insulator based scaffold for interfacing with cerebral organoids

Cerebral organoids are hSPC derived tissue complexes that self-organize over an extended period and begin to recapitulate certain features of in vivo neurogenesis, and there is a need to develop tools that allow for the physical and electrical interrogation of these cell complexes as they mature. Presented here is a method of manufacturing thin, porous, scalable silicon scaffolds as a structure to support multi-electrode arrays using industry standard semiconductor fabrication techniques. Mechanical tests by nanoindentation demonstrate the scaffold as linearly elastic with an approximated effective stiffness of 51.6 MPa. Biological cell studies indicate that mature Cerebral Organoids are capable of cellular expansion through, and partially absorbing, the scaffold, with 0.125 mm3 ± 0.027 of new tissue generation over a 5-day culture period. The structure is designed for compatibility with front end of line and back end of line semiconductor processes for future integration with metal electrodes, which enables deep tissue access in multi-cellular structures.

(Invited) Optical Biosensors in Photonic Integrated Circuits for Smart System Integration

Photonic integrated circuits (PIC) are like electronic integrated circuits drivers of communication systems. Moreover, state-of-the-art technologies enable the fabrication of electronic-photonic integrated circuits (ePIC), which allows for example the cointegration of ultra-fast BiCMOS devices with high speed photo detectors. Besides that, this technology provides an attractive platform for biosensors. They open the door for label-free detection of various analytes with high specificity and in real-time. This gives perspective to highly scalable and cost effective technologies for smart system integration of biosensors and electronic readouts to realize a true lab-on-a-chip application.We present the integration of optical biosensors in a Si-based PIC-technology. This comprises a front-end of line with optical waveguides, an integrated Ge-photodiode and a complete back-end of line consisting of three thin and two thick aluminum metal layers. The optical biosensor is integrated by opening the optical waveguide from the backside of the chip. In particular, we released a Si-based slot waveguide, which provides an enhanced evanescent field to interact with the analyte and hence to increase the sensitivity. The slot waveguide is incorporated in a ring resonator and we analyzed the wafer-level performance using the full width at half maximum, which allows us to assess the optical losses. Thermal sensing in a wide temperature range is investigated. In addition, a simple and cost-effective microfluidic is realized and we show initial results of the surface functionalization. Our work demonstrates the compatibility of a photonic biosensor with a photonic integrated circuit technology without any restriction to the standard FEOL and BEOL processing on the wafer front-side, while it keeps the inherent high sensitivity of evanescent-field sensing and opens a route towards smart system integration. Figure 1

Tunable-performance all-oxide structure field-effect transistor based atomic layer deposited Hf-doped In2O3 thin films.

The relocation of peripheral transistors from the front-end-of-line (FEOL) to the back-end-of-line (BEOL) in fabrication processes is of significant interest, as it allows for the introduction of novel functionality in the BEOL while providing additional die area in the FEOL. Oxide semiconductor-based transistors serve as attractive candidates for BEOL. Within these categories, In2O3 material is particularly notable; nonetheless, the excessive intrinsic carrier concentration poses a limitation on its broader applicability. Herein, the deposition of Hf-doped In2O3 (IHO) films via atomic layer deposition for the first time demonstrates an effective method for tuning the intrinsic carrier concentration, where the doping concentration plays a critical role in determine the properties of IHO films and all-oxide structure transistors with Au-free process. The all-oxide transistors with In2O3: HfO2 ratio of 10:1 exhibited optimal electrical properties, including high on-current with 249 µA, field-effect mobility of 13.4cm2V-1s-1, and on/off ratio exceeding 106, and also achieved excellent stability under long time positive bias stress and negative bias stress. These findings suggest that this study not only introduces a straightforward and efficient approach to improve the properties of In2O3 material and transistors, but as well paves the way for development of all-oxide transistors and their integration into BEOL technology.

Materials Quest for Advanced Interconnect Metallization in Integrated Circuits.

Integrated circuits (ICs) are challenged to deliver historically anticipated performance improvements while increasing the cost and complexity of the technology with each generation. Front-end-of-line (FEOL) processes have provided various solutions to this predicament, whereas the back-end-of-line (BEOL) processes have taken a step back. With continuous IC scaling, the speed of the entire chip has reached a point where its performance is determined by the performance of the interconnect that bridges billions of transistors and other devices. Consequently, the demand for advanced interconnect metallization rises again, and various aspects must be considered. This review explores the quest for new materials for successfully routing nanoscale interconnects. The challenges in the interconnect structures as physical dimensions shrink are first explored. Then, various problem-solving options are considered based on the properties of materials. New materials are also introduced for barriers, such as 2D materials, self-assembled molecular layers, high-entropy alloys, and conductors, such as Co and Ru, intermetallic compounds, and MAX phases. The comprehensive discussion of each material includes state-of-the-art studies ranging from the characteristics of materials by theoretical calculation to process applications to the current interconnect structures. This review intends to provide a materials-based implementation strategy to bridge the gap between academia and industry.

Performance comparison of vertically stacked nanosheet CFET and standard CMOS without and with parasitic channels

The threshold voltage regulation and the effect of parasitic channels are important issues in CFET. In this paper, the characteristics of the complementary field-effect transistor (CFET) were simulated based on a self-aligned vertically stacked nanosheet fabrication process at the 2 nm technology node by TCAD simulation. The electrical characteristics of CFET were matched by adjusting the metal work function. We analyzed the static characteristics and transient response, as well as the impact of the parasitic channel. Compared to standard CMOS with the same process, the switching threshold and noise margin of CFET are approximately equal to CMOS, but the power and speed are slightly better than CMOS because nFET and pFET of CFET share the same gate to have small parasitic capacitance. With the height of the parasitic channel increasing, the off-state current and parasitic capacitance of the device increase, but CFET suppresses the bad effect of the parasitic channel and changes less. CFET with the stacked nanosheet structure has greater advantages than CMOS, can tolerate the parasitic channel from the fabrication process, and improve performance in the perspective of front-end-of-line (FEOL).

Towards Complete Recovery of Circuit Degradation by Annealing With On-Chip Heaters

This work reports an on-chip heater structure fabricated in the Front End of Line (FEOL) on a versatile ring-oscillator (RO) array utilized to conduct statistical characterization of on-chip annealing of statically, i.e., Bias Temperature Instabilities (BTI), and dynamically, i.e., BTI-Hot Carrier Degradation (HCD), stressed ROs. The heater allows to reach local temperatures up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \text {T} = +{300}^{\circ }\text{C}$ </tex-math></inline-formula> in milliseconds. Accurate thermal modelling of the heater structure has been conducted demonstrating that the heat is homogenously distributed across the array area, resulting in a valuable tool for precise on-chip circuit anneal. Exploiting the on-chip heater features, sequential annealing tests with increasing duration have been conducted after accelerated degradation of RO circuits. Moreover, we report detailed relaxation maps that allow a thorough insight into the annealing behaviour of our circuits vs temperature and time. This can potentially be used to anneal ICs “on-line” to prolong their useful lifetime towards a more sustainable use.

Fault Diagnosis of Wafer Acceptance Test and Chip Probing Between Front-End-of-Line and Back-End-of-Line Processes

With the rapid development of the semiconductor industry, fault diagnosis is an important task in routine operations to determine the root cause for faults that occur. A tool in manufacturing processes is equipped with a wide variety of sensors that record different types of process data. Wafers being processed are accompanied by a considerable amount of process data as a multivariate time series. Identifying the key process parameters and the corresponding process operations where faults occur can be used to facilitate the tasks of monitoring the process, maintaining the stability of the process, and stabilizing wafer production yield. This article proposes a novel solution procedure for fault diagnosis of wafer acceptance test (WAT) and chip probing (CP) using machine learning (ML). Based on the process flow of wafers and the corresponding process data, a sampling method, called synthetic minority oversampling technique (SMOTE), is first used to augment classification models with an imbalanced process dataset, and the best-practice SMOTE ratio is sought by using four competitive classifiers. By means of principal component analysis (PCA), the original data are transformed into visualizations to explore the distributions of good and bad lots of wafers. Based on the comparison of the four classifiers used in the test, the proposed logistic regression with data augmentation (LR-SMOTE) performs best. The ten most important features identified by using the LR are collected to determine potential failure operations. The identified failures in operations returned by using the proposed solution procedure for fault diagnosis of WAT and CP were confirmed by the engineers who work in the domain. Note to Practitioners—In semiconductor manufacturing practice, during the WAT and CP, domain engineers need to trace upstream the key process parameters and the corresponding key operations in the front-end-of-line (FEOL) process if any faults are detected in the back-end-of-line (BEOL) process. In fact, the FEOL and the BEOL are located in completely separate plants with different clean room standards. Bridging the information gap between these two different processes merits thorough scrutiny. Another challenge posed by fault diagnosis of WAT and CP is that the total number of features (i.e., process parameters) involved in the FEOL can be tens of thousands, leading to an adverse effect of data sparsity on model building.

Bevel contamination management in 3D integration by localized SiO2 deposition

This paper investigates silicon oxide bevel deposition to manage contamination in 3D integration with intermediate Back-End Of Lines (iBEOL) levels. Bevel etching and cleaning techniques are now sufficiently mature to remove efficiently contamination on wafer bevel area. However, 3D integration with iBEOL could require encapsulating metal lines, which emerge on the bevel area. This paper explores the efficiency of bevel deposition to answer contamination issues in 3D integration. Films are deposited on the bevel area of 300 mm wafers thanks to a torus shaped Plasma Enhanced Chemical Vapor Deposition (PECVD) configuration allowing encapsulation of the last few mm of the wafer frontside, backside and the apex in a single processing step. Deposition is carried out at 350 °C from mixture of SiH4 and N2O at 2 Torr. When the gap between wafer and top insulator increases from 0.4 to 0.7 mm, the frontside deposition profile is shifted by 0.5 mm inward. In accordance with refractive index of 1.55 measured by ellipsometry, surface analysis by X-ray Photoelectrons Spectroscopy (XPS) show a film composition of SiO1.8N0.3 with a quasi-constant composition from 147 to 149 mm wafer radius. The film resistance, evaluated by wet etch in 2% HF, leads to Wet Etch Rate (WER) ratio to thermal oxide of 4–5. We demonstrate that such films are compatible with oxide bonding. Thanks to a proper integration scheme, minimal impact on the bonding edge quality with bonding limit of 147.7 mm on real product Complementary Metal Oxide Semiconductor with 4 Metal levels (CMOS+M4) is reported. Finally, the effectiveness of the strategy to keep the metallic contamination at 1 × 1010 at.cm-2 or below is verified by either specific Liquid Phase Decomposition bevel Inductively Coupled Plasma Mass Spectrometry (LPD bevel-ICPMS) on BEOL wafers or by Vapor Phase Decomposition (VPD)-ICPMS standard process control on Front-End Of Line (FEOL) wet tool just after having cleaned BEOL wafers.

(Digital Presentation) Research on Single Wafer RCA Clean in High Aspect Ratio Trenches

I ntroduction. High aspect ratio (AR) processes are widely used in front end of line (FEOL) IC manufacturing. Figure 1 depicts high (AR) trench cleaning process. Polymerization residues produced during the dry etch process will cause many problems such as STI voids in the follow-up process if the residues are not removed. This can lead to lower yield and reduction of chip life[1]. It is difficult to completely clean the residue inside trench with aspect ratio greater than 10.As shown in Figure.2, poor wetting of the liquid in the high AR trench, prevents the cleaning of the whole trench. Typically, the wafer surface can be easily cleaned, however residues remain inside of the trench. The cleaning of polymerization residues inside the trench and eliminating watermarks are the main issues in high (AR) cleaning processes. In this paper, we design an infiltration experiment, polymerization residues cleaning experiment and drying experiment to verify single wafer RCA clean performance on high (AR) trench processes. The verification of the single wafer RCA wafer clean is through yield data. Experimental. In the infiltration experiment, a layer of 500A SiO2 was grown on the high aspect ratios trench wafer. As shown in Table I, This was followed by treating the wafers with different process conditions on ACM single wafer tool. The remaining oxide thickness inside trench was measured by transmission electron microscope (TEM). Figure 3 shows experimental steps.In the polymerization residue cleaning experiment, 7 wafers with trenches after dry etching were treated with different chemical and process mode shown in Table II on ACM single wafer tool. The defect count was measured by the inline defect detection equipment and the scanning electron microscope.(SEM)In the drying experiment, high AR wafers were processed on an ACM single wafer tool, under different drying conditions. The trench wafer were then transferred into a vacuum bag and the air was evacuated. If there is no watermark on wafer surface within 15 minutes, we consider that the wafer has been dried in the macro level.Wafers were split between being cleaned by single wafer RCA clean and by bench RCA clean. The wafers are scanned for defect count on the wafer surface after the cleaning process for both the base line (bench) and the single wafer tool. Finally, we review yield on device completion to check results of single wafer and bench clean. Results. Table I shows the result of dHF infiltration experiment. When the pre rinse DIW time exceeds 30 seconds, the whole trench is soaked by DIW, allowing the dHF to permeate the whole trench, with oxide loss being similar from the top to the bottom of the trench.Table II shows the result of cleaning experiment. ACM Single wafer dHF+SC1 (mega) process can effectively clean the whole trench. Figure 4 and 5 shows defect map and SEM picture after single DHF+SC1(mega).Figure 6 shows the effect of chuck rotation speed and N2 flow rate on wafer drying. Figure 10 shows particle performance under different drying process conditions. Figure 7 shows the inline defect map and SEM after dry process.Figure 8 & 9 show the particle performance after the clean process. No special particle map appears with the single wafer clean process. Fig 10 shows the yield performance after all of the processes are completed. Average yield of single clean process is better than the baseline bench clean process. Table 3 shows detailed yield data from the wafer splits . Conclusion. Infiltration and cleaning experiment result shows that single wafer RCA clean can effectively clean the polymerization residues inside of high aspect ratio trenches. Dry experiment result shows that single wafer process can reduce watermark and particles in the dry step. Inline particle performance and final yield performance shows that single wafer RCA clean is better than baseline bench. Single wafer clean has lower standard deviation than bench clean and SW RCA clean in high (AR) trench process is feasible and effective. References. Xue. Research on High Aspect Ratio TSV Cleaning Technology enhanced by Megasonic[D]. Beijing: University of Chinese Academy of Sciences, 2016.JiHoon Cha, ChangSup Mun, etal. Low Si recess on cleaning process by dilute HF/SC-1 with megasonic[J]. Solid State Phenomena, 2008, 134:209-212.H Wang, Yue Ma, Fuping.Chen, etal. Removal of Fine Particle using SAPS Technology and Functional Water[J]. Solid State Phenomena, 2013, 195:185-190.Dae-Hong EOM, Geun-Bae LIM, etal. Reaction of Ozone and H2O2 in NH4OH Solutionsand Their Reaction with Silicon Wafers[J]. Japanese Journal of Applied Physics, 2004, 43:3335-3339. Figure 1

Via-Switch FPGA: 65-nm CMOS Implementation and Evaluation

Offering a combination of low latency, high energy-efficiency, and flexibility, field-programmable gate arrays (FPGAs) suit applications ranging from Internet of Things (IoT) computing to artificial intelligence (AI). The conventional static random access memory (SRAM) FPGAs face severe challenges including large standby power and low logic density due to utilization of SRAM cell and MOS switch for signal routing. In response, researchers have introduced emerging non-volatile (NV) memory technologies to solve standby power issues. However, access transistors used for NV memory cell configuration still consume a large silicon area. In this article, we introduce an NV via-switch (VS) FPGA featuring fully back-end-of-line (BEOL) signal routing and front-end-of-line (FEOL) logic computing for high logic density. The VS fabricated in BEOL is constructed by two Cu atom switches (ASs) for signal routing and two a-Si/SiN/a-Si varistors for AS configuration. We demonstrate the first implementation of the VS-FPGA at 65-nm node and evaluate its performance by various basic applications. 2.6 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> logic density, 1.5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> energy efficiency, and 1.4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> operation speed are achieved in comparison with a previous complementary AS (CAS) FPGA in which one access transistor is necessary for each CAS configuration.

CMOS-MEMS Thermal-Piezoresistive Resonators and Oscillators for Sensors

Microelectromechanical systems (MEMS) are in widespread commercial use due to their compact size, high performance, and low cost. MEMS resonators have emerged as front runners for sensing (accelerometers, gyroscopes, and particulate matter) and frequency (RF front-end, filters, timing, and frequency source) applications. The excellent stability, resolution, and accuracy of resonators lead them an ideal candidate for sensor implementation. The CMOS-MEMS technology allows for rapid, large-scale, and low-cost manufacturing. Thermal–piezoresistive resonators (TPRs) are promising candidates due to their favorable potential with scaling and robust performance in the ambient environment. A detailed finite element method (FEM) simulation flow is presented along with a mathematical model for device optimization. The devices were fabricated with the commercial CMOS technology utilizing the front-end-of-line (FEOL) polysilicon and back-end-of-line (BEOL) materials like silicon dioxide and interconnect metal. The flexibility of selective material placement in layout and complex routing using multi-metal interconnect is employed to develop a balanced TPR design at 2 MHz. A 5-MHz bulk mode TPR was designed for mass sensing application. The fabricated devices were characterized, and their performance is compared with other state-of-the-art works. Finally, the developed devices were used in real-world applications for mass sensing and pressure sensing. The device achieved 20 kHz/ng. The TPR devices combine principles of Pirani gauge and resonant sensors for improving the sensing range from 2 to 760 Torr (1 atm).

(Digital Presentation) Extending the Application of Capacitively Coupled Plasma Etching Tools to the Front-End-of-Line Fin-Cut Etching Process for FinFET Mass Production

As FinFET scales down to advanced technology nodes, Self-aligned Quadruple Patterning (SaQP) scheme is widely deployed for Fin formation, where two mandrels (MD1 and MD2) and corresponding mandrel spacers (MD1SP and MD2SP) are patterned for accurate CD transferring. The Fin-cut etching process of the MD2SP Cutting is very critical for the patterning of the Standard Cell and the SRAM patterns. This work studies the application of the Front End of Line (FEoL) MD2SP Cutting process in both inductively coupled plasma (ICP) and capacitively coupled plasma (CCP) etchers. The mismatch between the two tools is observed and discussed in detail. For CCP tools, a degradation of line width roughness (LWR) and increase of critical dimension (CD) loading between dense and isolated patterns are observed. Compared with the ICP etchers, the CCP etchers have lower plasma dissociation and stronger physical bombardment of ions. Furthermore, it is harder to control the plasma density and directionality separately. To increase CCP tool applications in FEoL processes, we introduce a Silicon coating process to modify the photoresist (PR) during the CCP etching to harden the surface of the PR and enhance the LWR performance. Furthermore, the application of atomic layer etching (ALE) technology ensures the CD loading between the dense and isolated patterns. With the application of our study, we can broaden the application of CCP tools in FEoL for FinFET mass production.

A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL

Split manufacturing was introduced as a countermeasure against hardware-level security threats such as IP piracy, overbuilding, and insertion of hardware Trojans. However, the security promise of split manufacturing has been challenged by various attacks which exploit the well-known working principles of design tools to infer the missing back-end-of-line (BEOL) interconnects. In this work, we define the security of split manufacturing formally and provide the associated proof, and we advocate accordingly for a novel, formally secure paradigm. Inspired by the notion of logic locking, we protect the front-end-of-line (FEOL) layout by embedding secret keys which are implemented through the BEOL in such a way that they become indecipherable to foundry-based attacks. At the same time, our technique is competitive with prior art in terms of layout overhead, especially for large-scale designs (ITC’99 benchmarks). Furthermore, another concern for split manufacturing is its practicality (despite successful prototyping). Therefore, we promote an alternative implementation strategy, based on package-level routing, which enables formally secure IP protection without splitting at all, and thus, without the need for a dedicated BEOL facility. We refer to this as “poor man’s split manufacturing” and we study the practicality of this approach by means of physical-design exploration.

Semiconductor wafer defect classification using convolution neural network: a binary case

With the multitude of steps used in semiconductor industry, automation is being practiced extensively in its manufacturing processes to guarantee quality of manufactured chips and improvement in production. At front end of line, wafer are probed and defective chips are segregated. From this data wafer bin map are generated, these show defects on the surface of wafers. If analysis of wafer bin map is done manually, this may result in incorrect categorization of defects due to human error and lack of judgement. Thus, the rationale behind this research study is to determine the scope of vision-based methods for automatic classification of wafer defects. In view of this, a classifier which detects Type A and Type B defects in wafers is proposed. It involves a Convolution Neural Network (CNN) based binary classifier. 250 Images of each class of wafer bin map dataset, is used to conduct the study on five layer CNN architecture. The proposed setup gives the test accuracy of 97.7%.

In-line Raman spectroscopy for gate-all-around nanosheet device manufacturing

In-line Raman spectroscopy for compositional and strain metrology throughout front-end-of-line (FEOL) manufacturing of next-generation gate-all-around nanosheet field-effect transistors is presented. Thin and alternating layers of fully strained pseudomorphic Si(1 − x)Gex and Si were grown epitaxially on a Si substrate and subsequently patterned. Intentional strain variations were introduced by changing the Ge content (x = 0.25, 0.35, 0.50). Polarization-dependent in-line Raman spectroscopy was employed to characterize and quantify the strain evolution of Si and Si(1 − x)Gex nanosheets throughout FEOL processing by focusing on the analysis of Si-Si and Si-Ge optical phonon modes. To evaluate the accuracy of the Raman metrology results, strain reference data were acquired by non-destructive high-resolution x-ray diffraction and from destructive lattice deformation maps using precession electron diffraction. It was found that the germanium-alloy composition as well as Si and Si(1 − x)Gex strain obtained by Raman spectroscopy are in very good agreement with reference metrology and follow trends of previously published simulations.

Investigation on the Effects of Interconnect RC in 3nm Technology Node Using Path-Finding Process Design Kit

With the continuous development of front-end-of-line (FEOL) technology, the development of interconnection processes at nanoscale process nodes is becoming important. We conducted a post-layout circuit simulation to consider the effect of parasitic R and C components of middle-of-Line (MOL) and back-end-of-line (BEOL) on the circuit performance. We constructed a process design kit (PDK) for path-finding to analyze the circuit layout in a 3nm technology node based on gate-all-around FET (GAA-FET). It consists of the spice model library that satisfies the 3nm power performance area (PPA) target, and the layout versus schematic (LVS), parasitic extraction (PEX) model that checks whether the layout and schematic match, extracts the RC values in the FEOL MOL and BEOL areas. Subsequently, the effect of the interconnection on complex logic circuits (RO, full adder) was confirmed using PDK. As a result of quantifying the effects of FEOL, MOL, and BEOL on the circuit, circuit degradation due to the RC of MOL and BEOL accounts for more than 60%. Furthermore, we introduced the air spacer process as a way to improve the circuit performance by reducing the CMOL owing to the reduction in the dielectric constant of the spacer. When an air spacer is introduced, based on 9-stages FO1 INV RO with k = 7 at V_DD = 0.7V, under iso-speed condition, the active power decreases by 30%, 35% when k is 3.3, 1.65, respectively. Under iso-power condition, frequency increases by 9%, 11% when k is 3.3, 1.65, respectively. And based on full adder with k = 7 at V_DD = 0.7V, Under iso-speed conditions, the active power decreases by 47%, 58% when k is 3.3, 1.65, respectively. Under iso-power conditions, the delay decreases by 14%, 20% when k is 3.3, 1.65, respectively. PDP decreases by 22%, 32% when k is 3.3, 1.65, respectively. EDP decreases by 31%, 44% when k is 3.3, 1.65, respectively. In conclusion, in this work, we provide a guide for determining the BEOL load and developing an improved wiring process.

Transistors based on two-dimensional materials for future integrated circuits

Field-effect transistors based on two-dimensional (2D) materials have the potential to be used in very large-scale integration (VLSI) technology, but whether they can be used at the front end of line or at the back end of line through monolithic or heterogeneous integration remains to be determined. To achieve this, multiple challenges must be overcome, including reducing the contact resistance, developing stable and controllable doping schemes, advancing mobility engineering and improving high-κ dielectric integration. The large-area growth of uniform 2D layers is also required to ensure low defect density, low device-to-device variation and clean interfaces. Here we review the development of 2D field-effect transistors for use in future VLSI technologies. We consider the key performance indicators for aggressively scaled 2D transistors and discuss how these should be extracted and reported. We also highlight potential applications of 2D transistors in conventional micro/nanoelectronics, neuromorphic computing, advanced sensing, data storage and future interconnect technologies.