Towards Complete Recovery of Circuit Degradation by Annealing With On-Chip Heaters

Abstract

This work reports an on-chip heater structure fabricated in the Front End of Line (FEOL) on a versatile ring-oscillator (RO) array utilized to conduct statistical characterization of on-chip annealing of statically, i.e., Bias Temperature Instabilities (BTI), and dynamically, i.e., BTI-Hot Carrier Degradation (HCD), stressed ROs. The heater allows to reach local temperatures up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \text {T} = +{300}^{\circ }\text{C}$ </tex-math></inline-formula> in milliseconds. Accurate thermal modelling of the heater structure has been conducted demonstrating that the heat is homogenously distributed across the array area, resulting in a valuable tool for precise on-chip circuit anneal. Exploiting the on-chip heater features, sequential annealing tests with increasing duration have been conducted after accelerated degradation of RO circuits. Moreover, we report detailed relaxation maps that allow a thorough insight into the annealing behaviour of our circuits vs temperature and time. This can potentially be used to anneal ICs “on-line” to prolong their useful lifetime towards a more sustainable use.