Performance comparison of vertically stacked nanosheet CFET and standard CMOS without and with parasitic channels

Abstract

The threshold voltage regulation and the effect of parasitic channels are important issues in CFET. In this paper, the characteristics of the complementary field-effect transistor (CFET) were simulated based on a self-aligned vertically stacked nanosheet fabrication process at the 2 nm technology node by TCAD simulation. The electrical characteristics of CFET were matched by adjusting the metal work function. We analyzed the static characteristics and transient response, as well as the impact of the parasitic channel. Compared to standard CMOS with the same process, the switching threshold and noise margin of CFET are approximately equal to CMOS, but the power and speed are slightly better than CMOS because nFET and pFET of CFET share the same gate to have small parasitic capacitance. With the height of the parasitic channel increasing, the off-state current and parasitic capacitance of the device increase, but CFET suppresses the bad effect of the parasitic channel and changes less. CFET with the stacked nanosheet structure has greater advantages than CMOS, can tolerate the parasitic channel from the fabrication process, and improve performance in the perspective of front-end-of-line (FEOL).