Front-end Circuit Research Articles

Multi-Channel Sensing System Utilizing Mott Memristors for Single-Wire Data Fusion and Back-End Greedy Strategy Data Recovery

This paper presents a novel Mott memristor-based multi-channel sensing system designed for the simultaneous processing of multiple sensing channels, employing single-wire data fusion and a greedy search strategy for back-end data recovery. Multiple channels of external stimulus information are simultaneously encoded into analog signals with varying frequencies, utilizing a Mott memristor array. Auxiliary circuits then convert the analog sensing signals into square wave signals which are further transformed into narrow (100 ns) pulse signals through pulse generation circuitry. Subsequently, these narrow pulse signals are fused into a single-wire signal by using an OR gate. At the back-end of the system, a greedy searching strategy is applied to accurately identify all frequencies within the fused pulse signal, enabling seamless analog-to-frequency conversion across multiple channels. The system is suitable for a wide range of sensors and can be directly connected to FPGAs for data processing, eliminating the need for traditional analogue front-end and ADC circuits and greatly reducing circuit complexity and power consumption. By leveraging the innovative capabilities of Mott memristors, the proposed system achieves precise analog-to-frequency conversion with significantly reduced power consumption.

Two Proposals of a Simple Analog Conditioning Circuit for Remote Resistive Sensors with a Three-Wire Connection.

This article proposes and experimentally characterizes two implementations of a novel front-end circuit for three-wire connected resistive sensors with a wire-resistance compensation. The first implementation relies on two twin diodes, whereas the second on a switch; in both cases, those devices are non-remote (i.e., they are placed at the circuit end). The two circuit proposals have a square-wave input excitation so that a constant current with the two polarities is alternatively generated. Then, depending on that polarity, the current goes through either the sensor and the wire parasitic resistances or just the parasitic resistances. This generates a square-wave bipolar output signal whose average value, which is obtained by a low-pass filter, is proportional to the sensor resistance and only depends on the mismatch between two of the three wire resistances involved. Experimental tests applied to resistances related to a Pt100 thermal sensor show a remarkable linearity. For example, the switch-based front-end circuit offers a non-linearity error lower than 0.01% full-scale span, and this is practically insensitive to both the presence and the mismatch between the wire resistances.

An 800MΩ-Input-Impedance 95.3dB-DR Δ-ΔΣ AFE for Dry-Electrode Wearable EEG Recording.

Non-invasive, closed-loop brain modulation offers an accessible and cost-effective means of evaluating and modulating one's mental and physical well-being, such as Parkinson's disease, epilepsy, and sleep disorders. However, wearable EEG systems pose significant challenges for the analog front-end (AFE) circuits in view of µV-level EEG signals of interest, multiple sources of interference, and ill-defined skin contact. This paper presents a direct-digitization AFE tailored for dry-electrode scalp EEG recording, characterized by wide input dynamic range (DR) and high input impedance. The AFE utilizes a second-order 5-bit delta-delta sigma (Δ-ΔΣ) ADC to shape DC electrode offset (DEO) and low-frequency disturbances while retaining high accuracy. A non-inverting pseudo-differential instrumentation amplifier (IA) embedded in the ADC ensures high input impedance (Zin) and common-mode rejection ratio (CMRR). Fabricated in a standard 0.18-μm CMOS process, the AFE delivers 700-mVpp input signal range, 95.3-dB DR, 87-dB SNDR, and 800-MΩ input impedance at 50 Hz while consuming 88.4µW from a 1.2 V supply. The benefits of high DR and high input impedance have been validated by dry-electrode EEG measurement.

Built-In Self-Test of Millimeter-Wave Integrated Front-End Circuits: How Far Have We Come?

Built-In Self-Test of Millimeter-Wave Integrated Front-End Circuits: How Far Have We Come?

An Isolation Amplifier-Based Front-End Circuit for Grounded Capacitive Sensors

An Isolation Amplifier-Based Front-End Circuit for Grounded Capacitive Sensors

High-precision time measurement electronics using the bandpass sampling method.

Waveform digitization at sampling rates up to several giga-samples per second is one of the approaches to achieve high-precision time measurements. In recent years, achieving high precision at lower sampling rates has emerged as a significant research topic. In this article, we focus on time measurement electronics, in which the bandpass sampling method is applied to obtain high precision at a sampling rate of roughly 100 MSps. An analog front-end circuit is designed, in which the input pulse signal is bandpass-filtered and amplified before sampling. A pipelined real-time time extraction algorithm is designed using the techniques of interpolation and cross correlation. A 1024-point fast Fourier transform algorithm is adopted to implement the cross correlation operation. Four time measurement channels are implemented in a mid-range field-programmable gate array, and the measurement rate of 116kHz is achieved. Tests are conducted to evaluate the performance of the timing system. The typical RMS precision is better than 0.4ps.

A wideband low power RF Receiver Front-End for Internet-of-Things applications

This paper presents a broadband RF receiver front-end circuit that offers advantages in both area and power consumption. The design features an innovative dual-path noise-canceling Low-Noise Amplifier (LNA) circuit, achieving impedance matching and balun functionality without the need for on-chip inductors. The RF receiver front-end circuit comprises a I and Q doublebalanced quadrature passive mixers and an 25% duty-cycle LO generator. The circuit’s broadband characteristics enable it to operate across a wide range of frequency bands. It is implemented using a 65 nm CMOS process. The core circuit, including both RF and baseband signal paths, consumes a mere 12 mW of power. Test results demonstrate that the RF receiver front-end circuit achieves a conversion gain of 35–40 dB, a noise figure (NF) below 4.8 dB, and a minimum third-order intercept point (IIP3) exceeding −6.8 dBm over the 0.1–3.1 GHz frequency range. The chip’s overall footprint is compact at 0.9 mm2, with the entire RF signal path powered by a 1 V supply, offering clear advantages in terms of compactness and low power consumption.

Design of a Configurable 4-Channel Analog Front-End for EEG Signal Acquisition on 180nm CMOS Process

In this work, a 4-channel Analog Front-End (AFE) circuit has been proposed for EEG signal recording. For EEG recording systems, the AFE may handle a wide range of sensor inputs with high input impedance, adjustable gain, low noise, and wide bandwidth. The buffer or current-to-voltage converter block (BCV), which can be set to operate as a buffer or a current-to-voltage converter circuit, is positioned between the electrode and the main amplifier stages of the AFE to achieve high input impedance and work with sensor signal types. A chopper capacitively-coupled instrumentation amplifier (CCIA) is positioned after the BCV as the main amplifier stage of the AFE to reduce input-referred noise and balance the impedance of the overall AFE system. A programmable gain amplifier (PGA) is the third stage of the AFE that allows the overall gain of the AFE to be adjusted. The suggested AFE operates in a wide frequency range of 0.5 Hz to 2 kHz with a high input impedance bigger than 2TΩ, and it is constructed and simulated using a 180nm CMOS process. With the lowest 100-dB CMRR and low input-referred noise of 1.8 µVrms, the AFE can achieve low noise efficiency. EEG signals can be acquired with this AFE system, which is very useful for detecting epilepsy and seizures.

Low-noise fast-response readout circuit to improve coincidence time resolution

Time-of-flight (TOF) PET detectors with fast-rise-time scintillators and fast-single photon time resolution silicon photomultiplier (SiPM) have been developed to improve the coincidence timing resolution (CTR) to sub-100 ps. The CTR can be further improved with an optimal bandwidth and minimized electronic noise in the readout circuit and this helps reduce the distortion of the fast signals generated from the TOF-PET detector. The purpose of this study was to develop an ultra-high frequency and fully-differential (UF-FD) readout circuit that minimizes distortion in the fast signals produced using TOF-PET detectors, and suppresses the impact of the electronic noise generated from the detector and front-end readout circuits. The proposed UF-FD readout circuit is composed of two differential amplifiers (time) and a current feedback operational amplifier (energy). The ultra-high frequency differential (7 GHz) amplifiers can reduce the common ground noise in the fully-differential mode and minimize the distortion in the fast signal. The CTR and energy resolution were measured to evaluate the performance of the UF-FD readout circuit. These results were compared with those obtained from a high-frequency and single ended readout circuit. The experiment results indicated that the UF-FD readout circuit proposed in this study could substantially improve the best achievable CTR of TOF-PET detectors.

Electrical impedance tomography: a review on hardware systems and circuits

Abstract Electrical impedance tomography (EIT) is a widely used functional imaging technology in the field of biomedical engineering with the characteristics of non-radiation, high temporal resolution, real-time, miniaturization, and low cost, but with relatively poor spatial resolution, which makes it become an effective complementary imaging alternative in conjunction with structural imaging technologies such as MRI and CT for bedside monitoring. The hardware systems and circuits (HSC) are the physical basis for EIT, and have major impacts on imaging speed, accuracy, cost and other key performance specifications. This review attempts to provide researchers with a relatively comprehensive picture of HSC for different EIT systems, which is organized as follows. Firstly, the general EIT hardware systems are classified as serial, fully parallel and semi-parallel types, respectively, according to their hardware architecture. Secondly, the main analogy front-end circuits of EIT hardware systems are summarized, in which the current drive circuits are divided into open loop, linear closed-loop and nonlinear closed-loop based on different feedback types. Thirdly, the common error sources and evaluation indicators on EIT measurements are summarized. Finally, the future development trends and research challenges of EIT are discussed. This review is expected to promote the development of EIT technology, especially on the design of HSC.

Second-Order Level-Crossing Sampling Analog to Digital Converter for Electrocardiogram Delineation and Premature Ventricular Contraction Detection.

This article presents an electrocardiogram (ECG) delineation and arrhythmia heartbeat detection system using a novel second-order level-crossing sampling analog to digital converter (ADC) for real-time data compression and feature extraction. The proposed system consists of the front-end integrated circuit of the data converter, the delineation algorithm, and the arrhythmia detection algorithm. Compared with conventional level-sampling ADCs, the proposed circuit updates tracking thresholds using linear extrapolation, which forms a second-order level-crossing sampling ADC that has sloped sampling levels. The computing is done digitally and is implemented by modifying the digital control logic of a conventional Successive-approximation-register (SAR) ADC. The system separates the sampling and quantization processes and only selects the turning points in the input waveform for quantization. The output of the proposed data converter consists of both the digital value of the selected sampling points and the timestamp between the selected sampling points. The main advantages are data savings for the data converter and the following digital signal processing or communication circuits, which are ideal for low-power sensors. The test chip was fabricated using a 180 nm CMOS process. When sensing sparse signals such as ECG signals the proposed ADC achieves a compression factor of 8.33. The delineation algorithm uses a triangle filter method to locate the fiducial points and measures the intervals, slopes, and morphology of the QRS complex and the P/T waves. Those extracted features are then used in the arrhythmia heartbeat detection algorithm to identify Premature Ventricular Contraction (PVC). The overall performance of the system is evaluated using the MIT-BIH database and the QT database, which is also compared with the recently reported systems. The accuracy, sensitivity, specificity, PPV, and F1 score are 97.3%, 89.6%, 97.8%, 73.3%, and 0.81 for detecting PVC.

Adjustable High-Power Light Emitting Diode Driving Circuit and Its Lighting Application in Sports Venues

High-power LED not only has the characteristics of energy saving, environmental protection, long service life, and high reliability, but also has the advantages of high light efficiency and large conduction current. According to the characteristics of high-power LED, an adjustable high-power LED driving circuit is designed in this study. The chip adopts the Boost circuit structure driven by constant current, and the output current on a single channel is converted into voltage by using the sampling resistor on the LED path and fed back to the circuit. After passing a mirror current independent of temperature through a resistor, the reference voltage source is obtained by voltage division. When designing the LDO circuit of voltage regulator, modules such as front-end voltage conversion circuit and input under voltage protection circuit are added. When designing the soft start circuit, the output voltage of the soft start replaces the output of the error amplifier and is connected to one end of the PWM comparator. In the design of dimming circuit, PWM dimming technology is adopted, and the DIM pin is connected to low level when there is no PWM signal. In the experiment, the lowest level of soft start is 0.78 V, the highest bit is 1.35 V, and the period is 374.6 us. When VIN = 8 V, the output voltage can be adjusted to 40 V in one period based on soft start, which meets the starting requirements of the driving circuit. When the DIM pin is connected with a PWM dimming signal with a duty ratio of 90% and a frequency of 10 kHz, the output current of the LED light is in a relatively stable state. Applying the designed LED driving circuit to the lighting of sports venues can meet the requirements of daily events and training, and has advantages in energy saving and environmental protection.

Modeling Method of Multiplexed Sampling Electrical Parameter Characteristics Based on AIOT Sensing Module

Abstract In order to further reduce the errors arising in synchronous sampling, this paper designs a multi-channel hybrid sampling electrical parametric feature modeling method based on an AIOT sensing module in the process of design. The AIOT sensing module is used to process the received RF signals using a transconductance amplifier to improve the digitization and reconfigurability of the RF front-end circuit. The signal is transformed and calculated using the Fast Fourier Transform to obtain electrical parameters such as the amplitude of each harmonic and the power factor. The results show that the variation amplitude of the window function of the design method in this paper is generally maintained between -1.5 and 1.5, the amplitude accuracy of the active power rate is within 3.17555%, and the relative error accuracy is within 0.000951%. It can be seen that the AIOT-based sensing module can significantly improve the calculation accuracy of electrical parameters and can be applied to the process of sampling digital measurements of other power signal characteristics.

ECG Signal Acquisition and Processing System

This paper mainly designs an ECG signal acquisition and processing acquisition system, which mainly includes two parts: an ECG acquisition front-end circuit module and a LabVIEW processing and display module. The front-end circuit of ECG acquisition mainly consists of amplifying and filtering modules, which are used to collect and process human signals in real time. In addition, a charging box circuit is designed at the same time, which can charge the ECG monitoring equipment while storing energy and increase the standby time of the equipment. At the same time, the acquired signal is filtered in LabVIEW, and the baseline drift is eliminated to obtain a cleaner and clearer ECG waveform.

Front-End Circuit for Photomultiplier Tube Signal Readout Based on Recognition of Traffic Signal Images

Photoelectric sensing technology plays a crucial role in vehicular equipment, which is equipped with various photoelectric devices to perceive the surrounding environment and avoid traffic lights and vehicles. This research selects the Hamamatsu H9500, a 256-channel, position-sensitive photomultiplier tube, as the test unit. It aims to simplify signal readout while improving the spatial resolution of the photodetector. This research focuses on designing a charge distribution circuit named Discretized Positioning Circuit (DPC) for the photomultiplier tube, with an additional charge-sensitive front-end amplification and shaping circuit. This circuit can convert the weak current signals from the H9500 into voltage signals. The shaping part of the circuit employs an active CR-RC circuit with weak signal amplification capabilities. This circuit is deployed within the photomultiplier tube, strategically positioned on vehicles to recognize various traffic sign images. The front-end shaping circuit is tested in the experiments, which converts square wave voltage into pulse current using a capacitor. It is observed that the current signal has a certain width and the voltage waveform of the CR differential circuit can be obtained by increasing the input impedance to 1 MΩ. During input voltage amplitude testing, the corrected output signal voltage shows a good linear relationship with the input square wave voltage. This designed front-end shaping circuit is used for signal readout in photomultiplier tubes and deployed in vehicular equipment to collect image information of traffic signs. After image processing, satisfactory recognition results are achieved.

Design of preamplifier circuit for ECG circuit of wearable devices

In this study, a wearable electrocardiogram (ECG) acquisition system with high performance instrumentation amplifier is presented. It adopts a 3-op-amp circuit and utilizes 180nm CMOS technology to achieve large input impedance. Furthermore, a drive-right leg module is used to configure the input’s common-mode range, increasing the common-mode rejection rate. Simulations in standard 180nm CMOS technology show bandwidths ranging from 0.1Hz to 251Hz. The front-end circuit operates on a 0.8V power supply. At the same time, using LTspice to conduct a preliminary test on the performance of the circuit, the total integrated input-referred noise of the circuit is 3.98 µVRMS , and the power consumption is 5.059 µ W . This satisfies the need for an ECG circuit with low power and noise requirements for wearable technology. The preliminary research findings presented in this paper have established a solid theoretical framework for the amplifier used in the measuring of ECG signals.

A High Efficiency 14–28 Gb/s Tunable Receiver Analog Front-End in 65 nm CMOS Technology

This work presents a tunable receiver analog front-end (AFE) circuit, capable of achieving data rates between 14 Gb/s and 28 Gb/s. The circuit is implemented using the TSMC 65 nm CMOS technology. The circuit incorporates a continuous-time linear equalizer (CTLE), a transimpedance amplifier (TIA) and an output buffer. A [Formula: see text]-boosted technique is employed within the CTLE for bandwidth and gain enhancement, while the TIA leverages a super source follower (SSF) structure to combat parasitic output node issues. By adjusting the tunable structures in the circuit, the proposed AFE can achieve variable DC gain at 14 GHz. Simulation results reveal that the AFE can compensate for the channel loss at the 14 GHz Nyquist frequency, delivering eye diagram spreads of approximately 0.85 UI and 0.78 UI at 14 Gb/s and 28 Gb/s, respectively. The complete post-simulation layout area is only 0.0026[Formula: see text]mm2. Operating with a power consumption of 10.5[Formula: see text]mW, the AFE exhibits an exceptional FoM of 11.8 pJ/bit/dB.

An accurate circuit model of Ge/Si single photon avalanche diode

Ge/Si single-photon avalanche diodes (SPADs) have benefits of low after-pulsing probability, low-cost and compatibility with CMOS electronics compared to InGaAs/InP counterpart, thus presenting great potentials for imaging and optical quantum applications in short-wave infrared (SWIR). In this work, an equivalent circuit model mimicking the behavior of pseudo-planar Ge/Si SPAD is constructed to provide accurate electronic information for the co-design of front-end circuit. The DC properties are modelled by nonlinear resistors, voltage-controlled switches and voltage sources, and the AC characteristics are emulated by junction and stray capacitances. To accurately evaluate the statistical behavior, thermal excitation and trap-assisted tunneling are incorporated in the built SPAD circuit models, where three-level traps are adopted to effectively fit the after-pulsing probability. The key model parameters such as electric field profile, breakdown voltage and avalanche triggering probability, are extracted from 2D device simulation. The developed Ge/Si SPAD circuit model implemented in Verilog-A hardware description language (HDL) with a gated passive quenching/reset architecture is validated by circuit simulation platform. The simulation results are in good agreement with the previously reported measurement data, demonstrating the effectiveness and accuracy of our Ge/Si SPAD circuit model.

A Front-End Circuit for Two-Wire Connected Resistive Sensors with a Wire-Resistance Compensation.

In this article, a novel front-end circuit for remote two-wire resistive sensors that is insensitive to the wire resistances is proposed and experimentally characterized. The circuit relies on an OpAmp-based current source with a square-wave excitation, two twin diodes in the feedback path, and a low-pass filter at the output. Using such a circuit topology, the output is a DC voltage proportional to the sensor resistance and independent of the wire resistances. A prototype was built measuring resistances that correspond to a Pt100 thermal sensor and with different values of wire resistance. The experimental results show that the output voltage is almost insensitive to both the wire resistances and their mismatch, with a relative error (with respect to the case with null parasitic resistance) in the range of 0.01-0.03% Full-Scale Span (FSS). In addition, the proposed circuit shows a remarkable linearity (around 0.01% FSS), and again this is independent of the presence and also of the mismatch of the wire resistances.

A Fast Interface Circuit for the Measurement of 10 Ω to 1 GΩ Resistance

In this work, an interface circuit applied to resistive gas or chemical sensors is proposed. The interface circuit includes a detection front-end, a single-end to differential circuit, a successive approximation analog-to-digital converter (SAR ADC), and some reference auxiliary circuits. In detection front-end circuits, mirrored currents in a current mirror usually differ by several orders of magnitude. In order to ensure that the current mirror can be copied accurately, this work uses a negative feedback structure consisting of an operational amplifier and an NMOS tube to ensure that the VDS of the current mirroring tube remains consistent. Simulation results show that the replication error of the current mirror is 0.015%. The proposed interface circuit has a detection range of 10 Ω to 1 GΩ with a relative error of 0.55%. The current multiplication or divided technique allows the interface circuit to have a high sampling frequency of up to 10 kHz. The proposed circuit is based on a 180 nm CMOS process with a chip area of 0.308 mm2 (723 μm ∗ 426 μm). The power consumption of the whole interface circuit is 3.66 mW when the power supply voltage is 1.8 V.