Electrical impedance tomography: a review on hardware systems and circuits

Abstract

Abstract Electrical impedance tomography (EIT) is a widely used functional imaging technology in the field of biomedical engineering with the characteristics of non-radiation, high temporal resolution, real-time, miniaturization, and low cost, but with relatively poor spatial resolution, which makes it become an effective complementary imaging alternative in conjunction with structural imaging technologies such as MRI and CT for bedside monitoring. The hardware systems and circuits (HSC) are the physical basis for EIT, and have major impacts on imaging speed, accuracy, cost and other key performance specifications. This review attempts to provide researchers with a relatively comprehensive picture of HSC for different EIT systems, which is organized as follows. Firstly, the general EIT hardware systems are classified as serial, fully parallel and semi-parallel types, respectively, according to their hardware architecture. Secondly, the main analogy front-end circuits of EIT hardware systems are summarized, in which the current drive circuits are divided into open loop, linear closed-loop and nonlinear closed-loop based on different feedback types. Thirdly, the common error sources and evaluation indicators on EIT measurements are summarized. Finally, the future development trends and research challenges of EIT are discussed. This review is expected to promote the development of EIT technology, especially on the design of HSC.