Front-end Application Specific Integrated Circuit Research Articles

The CMS Fast Beam Condition Monitor for HL-LHC

The high-luminosity upgrade of the LHC brings unprecedented requirements for real-time and precision bunch-by-bunch online luminosity measurement and beam-induced background monitoring. A key component of the CMS Beam Radiation, Instrumentation and Luminosity system is a stand-alone luminometer, the Fast Beam Condition Monitor (FBCM), which is fully independent from the CMS central trigger and data acquisition services and able to operate at all times with a triggerless readout. FBCM utilizes a dedicated front-end application-specific integrated circuit (ASIC) to amplify the signals from CO2-cooled silicon-pad sensors with a timing resolution of a few nanoseconds, which enables the measurement of the beam-induced background. FBCM uses a modular design with two half-disks of twelve modules at each end of CMS, with four service modules placed close to the outer edge to reduce radiation-induced aging. The electronics system design adapts several components from the CMS Tracker for power, control and read-out functionalities. The dedicated FBCM23 ASIC contains six channels and adjustable shaping time to optimize the noise with regards to sensor leakage current. Each ASIC channel outputs a single binary high-speed asynchronous signal carrying time-of-arrival and time-over-threshold information. The chip output signal is digitized,encoded, and sent via a radiation-hard gigabit transceiverand an optical link to the back-end electronics for analysis. This paper reports on the updated design of the FBCM detector and the ongoing testing program.

Time and Energy Resolving Time-over-Threshold ASIC for MPPC module in TOF-PET system (ToT-ASIC2)

ToT-ASIC2 is a new custom front-end application specific integrated circuit (ASIC) to readout silicon photomultiplier (SiPM) and multi-pixel photon counter (MPPC) for time-of-flight positron emission tomography (ToF-PET). ToT-ASIC2 is a 64-channel ASIC fabricated using a commercial 0.25 μm CMOS process. Each channel has an input-current buffer that sends signals to the SLOW and FAST paths, which are used for incident radiation energy and timing information, respectively. Time-over-Threshold (ToT) signals from these paths are combined into one ToT signal to be output outside the ASIC. The power consumption is approximately 2.9 mW per channel.This study developed a detection system comprising an MPPC with coupled GAGG pixelated scintillators, a front-end board with ToT-ASIC2 and ToT-DAQ. Consequently, energy and timing measurement experiments were performed using this system to confirm the ToT-ASIC2 energy- and timing-resolving capability. Prototype positron emission tomography experiments with 22Na indicated an energy resolution of 6.7% for 511 keV with the coincidence timing resolution being 215 ps.

A High Time-Resolved Front-End ASIC for APD Array Detector in Nuclear Resonant Scattering Experiments With Synchrotron Radiation

A high time-resolved front-end readout chip has been developed for avalanche-photodiode (APD) array detectors in nuclear resonant scattering (NRS) experiments. The chip has eight channels. Each channel consists of a preamplifier, a voltage discriminator, an open-drain output driver, and a local digital-to-analog converter (LDAC). The application-specific integrated circuit (ASIC) chip has been designed and fabricated in a 0.13- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology with a chip size of 1.1 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times2.3$ </tex-math></inline-formula> mm. The electrical characterizations of all eight channels demonstrate good time resolution (TR) (rms) on the output pulse leading edge, with the measurement result better than 25 ps for high input signal charges (>30 fC) and better than 98 ps for low input signal charges (8–30 fC), for an APD sensor capacitance as large as 15 pF. The equivalent noise charge (ENC) received from the measurement can be represented as ENC = 592.4 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−</sup> + 50.7 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−</sup> /pF. The power consumption is 17.6 mW per channel: 2.7 mW for the preamplifier–discriminator stage and 14.9 mW for the output low-voltage differential signaling (LVDS) driver.

Waveform processing using neural network algorithms on the front-end electronics

In a multi-channel radiation detector readout system, waveform sampling, digitization, and raw data transmission to the data acquisition system constitute a conventional processing chain. The deposited energy on the sensor is estimated by extracting peak amplitudes, area under pulse envelopes from the raw data, and starting times of signals or time of arrivals. However, such quantities can be estimated using machine learning algorithms on the front-end Application-Specific Integrated Circuits (ASICs), often termed as “edge computing”. Edge computation offers enormous benefits, especially when the analytical forms are not fully known or the registered waveform suffers from noise and imperfections of practical implementations. In this work, we aim to predict peak amplitude from a single waveform snippet whose rising and falling edges containing only 3 to 4 samples. We thoroughly studied two well-accepted neural network algorithms, Multi-Layer Perceptron (MLP) and Convolutional Neural Network (CNN) by varying their model sizes. To better fit front-end electronics, neural network model reduction techniques, such as network pruning methods and variable-bit quantization approaches, were also studied. By combining pruning and quantization, our best performing model has the size of 1.5 KB, reduced from 16.6 KB of its full model counterpart. It can reach mean absolute error of 0.034 comparing to that of a naive baseline of 0.135. Such parameter-efficient and predictive neural network models established feasibility and practicality of their deployment on front-end ASICs.

A Custom Low-Noise Silicon Photodiode Detector Designed for Use With X-Ray Capillary Optics

We present the first results of a custom low-noise silicon photodiode detector designed for use with X-ray capillary optics. This system is intended to perform as a smaller, lighter, and low-powered alternative to currently existing X-ray telescope technologies. The detector has an active area with a diameter of 100 μm, and its small size leads to a low capacitance of well under 1 pF and a leakage current of 1 pA or less at the depletion voltage. We tested the detector with both a discrete preamp and an ultralow-noise front-end application-specific integrated circuit (ASIC). The front-end ASIC, developed at Brookhaven National Laboratory, was designed for low-capacitance detectors but had not been previously tested with a detector. Here, we discuss the detector design, the experimental setup, and the resulting detector performance. Using radioactive laboratory sources, we measure a full-width at half-maximum (FWHM) of 211 ± 8 eV at 5.9 keV with the ASIC and are able to set the threshold as low as 0.6 keV.

A 12-bit 30 MS/s SAR ADC in 180 nm CMOS for PMT signal readout

Photomultiplier Tubes (PMTs) are widely used as the photon detector in high energy physics experiments for their fast response and high sensitivity. High precision charge measurement is usually required for PMT readout, and especially in cosmic ray experiments a large dynamic range is also demanded. This paper describes an Analog-to-Digital Converter (ADC) Application Specific Integrated Circuit (ASIC), which aims to work with a front-end analog ASIC to perform charge measurement based on the digital peak detection method. This ADC design is based on the power-efficient Successive Approximation Register (SAR) architecture, to achieve a 12-bit resolution with a sampling rate of up to 30 MS/s. Test results indicate that the Effective Number of Bits (ENOB) of this ADC is better than 9.2 bits with a sampling rate of 30 MS/s.

Miniaturized USB-powered multi-channel module for gamma spectroscopy and imaging

LAILA is a miniaturized eight-channel electronic readout system for compact γ-ray detectors, combining high-resolution spectroscopy capability with position sensitivity. Compactness is achieved by the combination of a novel CMOS front-end ASIC (Application-Specific Integrated Circuit) for analog processing of a large signal current from Silicon PhotoMultiplier (SiPM) solid-state photodetectors, with a microcontroller-based data acquisition system. The adoption of automatic gain regulation in the gated-integrator stage of the ASIC offers an 84 dB dynamic range, combining single-photon sensitivity with an extended input photon energy range (20 keV-4MeV, using 30 μm-cell SiPMs). Using this module with properly merged 144 SiPM pixels coupled to a 3 in.-thick lanthanum bromide scintillation crystal, a 3% energy resolution at 662 keV and 1cm spatial resolution in the estimation of the interaction coordinates are experimentally demonstrated in this work.

Development of a front-end ASIC for silicon-strip detectors of the J-PARC muon [formula omitted]/EDM experiment

A front-end application specific integrated circuit (ASIC) with high rate capability and deep memory buffer is needed for the silicon-strip detector for the J-PARC muon g−2/EDM experiment. In this experiment, we reconstruct a positron track from muon decay by the silicon-strip detector and measure the muon anomalous magnetic moment and the electric dipole moment precisely to explore new physics beyond the Standard Model. The front-end ASIC is required to tolerate hit rates of 1.4 MHz per strip, to be stable to the change of hit rate by a factor of 150 from the beginning to the end of the measurement, and to have deep memory for the period of 40μs with 5 ns time resolution. To satisfy the experimental requirements, we designed a prototype ASIC “SliT128B” with the Silterra 180 nm CMOS technology. We report on the design and the performance of the SliT128B.

Development of a High-Rate Front-End ASIC for X-Ray Spectroscopy and Diffraction Applications

-We developed a new front-end application-specific integrated circuit (ASIC) to upgrade the Maia X-ray microprobe. The ASIC instruments 32 configurable channels that perform either positive or negative charge amplification, pulse shaping, peak amplitude, and time extraction along with buffered analog storage. At a gain of 3.6 V/fC, 1-μs peaking time, and a temperature of 248 K, an electronic resolution of 13 and 10 e- rms was measured with and without a silicon drift detector (SDD) sensor, respectively. A spectral resolution of 170-eV full-width at half-maximum (FWHM) at 5.9 keV was obtained with an 55Fe source. The channel linearity was better than ± 1% with rate capabilities up to 40 kcps. The ASIC was fabricated in a commercial 250-nm process with a footprint of 6.3 mm × 3.9 mm and dissipates 167 mW of static power.

Miniaturized 0.13-μm CMOS Front-End Analog for AlN PMUT Arrays.

This paper presents an analog front-end transceiver for an ultrasound imaging system based on a high-voltage (HV) transmitter, a low-noise front-end amplifier (RX), and a complementary-metal-oxide-semiconductor, aluminum nitride, piezoelectric micromachined ultrasonic transducer (CMOS-AlN-PMUT). The system was designed using the 0.13-μm Silterra CMOS process and the MEMS-on-CMOS platform, which allowed for the implementation of an AlN PMUT on top of the CMOS-integrated circuit. The HV transmitter drives a column of six 80-μm-square PMUTs excited with 32 V in order to generate enough acoustic pressure at a 2.1-mm axial distance. On the reception side, another six 80-μm-square PMUT columns convert the received echo into an electric charge that is amplified by the receiver front-end amplifier. A comparative analysis between a voltage front-end amplifier (VA) based on capacitive integration and a charge-sensitive front-end amplifier (CSA) is presented. Electrical and acoustic experiments successfully demonstrated the functionality of the designed low-power analog front-end circuitry, which outperformed a state-of-the art front-end application-specific integrated circuit (ASIC) in terms of power consumption, noise performance, and area.

Positron tracking detector for J-PARC muon [formula omitted]/EDM experiment

The positron tracking detector is developed for the J-PARC muon g−2/EDM (E34) experiment. It uses silicon strip sensors for positron detection and signals from sensors are transferred to the front-end readout system via flexible printed circuits (FPCs) glued on the sensors. The front-end readout system consists of application specific integrated circuits (ASICs) on FPCs and the field-programmable gate array (FPGA)-based readout board. Mass production of silicon strip sensors is ongoing. Designs of the FPC on the sensor and the front-end ASIC were fixed and their mass production has been started. Development of other detector components are also ongoing. The status of these developments and fabrications are presented.

A Monolithic 32-Channel Front End and DSP ASIC for Gaseous Detectors

Conseil Européen pour la Recherche Nucléaire is currently undergoing a major upgrade within the A Large Ion Collider Experiment (ALICE) detectors, one of the four main experiments at the Large Hadron Collider (LHC) accelerator. The LHC luminosity will increase making the heavy ions collision rate rise from 500 Hz to 50 kHz. Both the time projection chamber (TPC) and muon chamber (MCH) detectors demand a new and faster readout electronics, which support continuous readout to cope with this higher rate. This paper presents the serialized analog-digital multipurpose application-specific integrated circuit (ASIC) (SAMPA) integrated circuit for upgrading the TPC and MCH front-end and signal processing of charge induced signals, addressing the higher data rate specification. The SAMPA comprises 32 equal channels, twice the present ALICE TPC readout circuitry capacity. Each channel is composed of a positive/negative polarity charge sensitive amplifiers, a pulse shaper, and a 10-bit analog-to-digital converter. It also integrates a full custom digital signal processor, which receives the data from 32 channels, compensate signal perturbations or distortion through several filters and transmits the processed data. Designed for Taiwan Semiconductor Manufacturing Company 130-nm CMOS process, the manufactured chip occupies an area of approximately 85 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes about 8.3 mW per channel at a nominal voltage supply of 1.25 V. The SAMPA is silicon proven and the experimental test results have confirmed its functionality and suitability for the ALICE Upgrade (2019-2020).

Front-end ASIC for spectroscopic readout of virtual Frisch-grid CZT bar sensors

Compact multi-channel radiation detectors rely on low noise front-end application specific integrated circuits (ASICs) to achieve high spectral resolution. Here, a new ASIC developed to readout virtual Frisch-grid cadmium zinc telluride (VFG CZT) detectors for gamma ray spectroscopy is presented. Corresponding to each ionizing event in the detector, the ASIC measures the amplitude and timing at the anode, the cathode and four pad sense electrodes associated with each sensor in a detector array. The ASIC is comprised of 52 channels of which there are 4 cathode channels and 48 channels which can be configured as either anode channels with a baseline of 250 mV or pad sense channels to process induced signals with a baseline of 1.2 V. With a static power dissipation of 3 mW, each channel performs low-noise charge amplification, high-order shaping, peak and timing detection along with analog storage and multiplexing. The overall channel linearity was better than $\pm$ 1 % with timing resolution down to 700 ps for charges greater than 8 fC in the 3 MeV range. With a 4 x 4 array of 6 mm x 6 mm x 20 mm virtual Frisch-grid bar sensors connected and biased, an electronic resolution of $\approx$ 270 rms $e^{-}$ for charges up to 100 fC in the 3.2 MeV range was measured. Spectral measurements obtained with the 3D correction technique demonstrated resolutions of 1.8 % FWHM at 238 keV and 0.9 % FWHM at 662 keV.

A Power Adaptive, 1.22-pW/Hz, 10-MHz Read-Out Front-End for Bio-Impedance Measurement

This paper presents a read-out front-end application-specific integrated circuit (ASIC) for the measurement of tissue impedances. The 10 mm2 2-channel front-end ASIC is fabricated in a 0.18μm CMOS technology. The measurement results show that the proposed ASIC operates over a frequency range of 100Hz up to 10MHz. The ASIC has 1.22 pW/Hz power performance, with an SNR over 72dB for frequencies ≤ 1MHz, and over 65dB SNR for frequencies ≥ 1MHz. The total measured power consumption of the read-out front-end is shown to range from 2.1 to 21.7 mW depending on the input frequency. To achieve a wide dynamic range, the instrumentation amplifier has an adaptive gain control feature, and it employs programmable bias currents and reconfigurable structure to save power while processing low-frequency signals. A dual digital-to-analog converter (DAC) hybrid SAR analog-to-digital converter (ADC) is presented that reduces the power consumption of the ADC driver by sevenfold for frequencies between 4 kHz and 1MHz.

P.1.05 Parcellation of the cerebral cortex based on messenger ribonucleic acid gene expressions

The positron tracking detector is developed for the J-PARC muon g−2/EDM (E34) experiment. It uses silicon strip sensors for positron detection and signals from sensors are transferred to the front-end readout system via flexible printed circuits (FPCs) glued on the sensors. The front-end readout system consists of application specific integrated circuits (ASICs) on FPCs and the field-programmable gate array (FPGA)-based readout board. Mass production of silicon strip sensors is ongoing. Designs of the FPC on the sensor and the front-end ASIC were fixed and their mass production has been started. Development of other detector components are also ongoing. The status of these developments and fabrications are presented.

A Reduced-Wire ICE Catheter ASIC With Tx Beamforming and Rx Time-Division Multiplexing.

This paper presents a single chip reduced-wire active catheter application-specific integrated circuit (ASIC), equipped with programmable transmit (Tx) beamforming and receive (Rx) time-division multiplexing (TDM). The proposed front-end ASIC is designed for driving a 64-channel one-dimensional transducer array in intracardiac echocardiography (ICE) ultrasound catheters. The ASIC is implemented in 60 V 0.18-μmHV-BCD technology, integrating Tx beamformers with high voltage pulsers and Rx front end in the same chip, which occupies 2.6 × 11 mm2 that can fit in the catheter size of 9F (<3 mm). The proposed system reduces the number of wires from >64 to only 22 by integrating Tx beamformer that is programmable using a single low-voltage differential signaling data line. In Rx mode, the system uses 8:1 TDM with direct digital demultiplexing providing raw channel data that enables dynamic Rx beamforming using individual array elements. This system has been successfully used for B-mode imaging on standard ultrasound phantom with 401 mW of average power consumption. The ASIC has a compact element pitch-matched layout, which is also compatible with capacitive micromachined ultrasound transducer on CMOS application. This system addresses cable number and dimensional restrictions in catheters to enable ICE imaging under magnetic resonance imaging by reducing radio frequency induced heating.

A Compact Detector Module Design Based on FlexToT ASICs for Time-of-Flight PET-MR

Recent developments in radiation detection technology have demonstrated the feasibility of simultaneous magnetic resonance imaging (MRI) and time-of-flight positron emission tomography (TOF-PET). In this paper we report on a compact detector module design for TOF-PET compatible with MR based on the FlexToT front-end application specific integrated circuit (ASIC), a fast, low-power front-end readout for silicon photomultiplier arrays. The module comprises scintillators, photosensors, ASICs, field-programmable gate arrays, and USB or Ethernet protocols for communication with data acquisition systems. The small footprint of the proposed design allows its use on positron emission tomography (PET) inserts for existing MRI equipment, both whole-body scanners, and dedicated organ systems. The main design features are presented together with results from the characterization of a proof-of-concept prototype in terms of radiation detection and measurements of radio frequency emission spectra from the electronic components. Ongoing work is focused on implementing and characterizing a full module inside MRI for ensuring electromagnetic compatibility, addressing proper shielding, and the possibility of simultaneous PET-MR acquisition using our compact detector module design.

A Human-Machine Interface Using Electrical Impedance Tomography for Hand Prosthesis Control.

This paper presents a human-machine interface that establishes a link between the user and a hand prosthesis. It successfully uses electrical impedance tomography, a conventional bio-impedance imaging technique, using an array of electrodes contained in a wristband on the user's forearm. Using a high-performance analog front-end application specific integrated circuit (ASIC), the user's forearm inner bio-impedance redistribution is accurately assessed. These bio-signatures are strongly related to hand motions and using artificial neural networks, they can be learned so as to recognize the user's intention in real time for prosthesis operation. In this work, eleven hand motions are designed for prosthesis operation with a gesture switching enabled sub-grouping method. Experiments with five subjects show that the system can achieve 98.5% accuracy with a grouping of three gestures and an accuracy of 94.4% with two sets of five gestures. The ASIC comprises a current driver with common-mode reduction capability and a current feedback instrumentation amplifier (that occupy an area of 0.07 mm2). The ASIC operates from ±1.65 V power supplies and has a minimum bio-impedance sensitivity of 12.7 mΩp-p.

A 2-D Ultrasound Transducer With Front-End ASIC and Low Cable Count for 3-D Forward-Looking Intravascular Imaging: Performance and Characterization

Intravascular ultrasound (IVUS) is an imaging modality used to visualize atherosclerosis from within the inner lumen of human arteries. Complex lesions like chronic total occlusions require forward-looking IVUS (FL-IVUS), instead of the conventional side-looking geometry. Volumetric imaging can be achieved with 2-D array transducers, which present major challenges in reducing cable count and device integration. In this work, we present an 80-element lead zirconium titanate matrix ultrasound transducer for FL-IVUS imaging with a front-end application-specific integrated circuit (ASIC) requiring only four cables. After investigating optimal transducer designs, we fabricated the matrix transducer consisting of 16 transmit (TX) and 64 receive (RX) elements arranged on top of an ASIC having an outer diameter of 1.5 mm and a central hole of 0.5 mm for a guidewire. We modeled the transducer using finite-element analysis and compared the simulation results to the values obtained through acoustic measurements. The TX elements showed uniform behavior with a center frequency of 14 MHz, a -3-dB bandwidth of 44%, and a transmit sensitivity of 0.4 kPa/V at 6 mm. The RX elements showed center frequency and bandwidth similar to the TX elements, with an estimated receive sensitivity of /Pa. We successfully acquired a 3-D FL image of three spherical reflectors in water using delay-and-sum beamforming and the coherence factor method. Full synthetic-aperture acquisition can be achieved with frame rates on the order of 100 Hz. The acoustic characterization and the initial imaging results show the potential of the proposed transducer to achieve 3-D FL-IVUS imaging.

Design and Testing of the Address in Real-Time Data Driver Card for the Micromegas Detector of the ATLAS New Small Wheel Upgrade

The address in real-time data driver card (ADDC) is designed to transmit the trigger data in the micromesh gaseous structure (Micromegas, MM) detector of the ATLAS new small wheel (NSW) upgrade. The address in real-time (ART) signals are generated by the front-end application-specific integrated circuit (ASIC), named VMM chip, to indicate the address of the first above-threshold event. A custom ASIC (ART ASIC) is designed to receive the ART signals from the VMM chip and implement the hit selection. The processed data from the ART ASIC will be transmitted out of the NSW through the gigabit transceiver (GBTx) serializer, the unidirectional versatile twin transmitter (VTTx), and fiber-optic links. The ART signal is critical for the ATLAS experiment trigger selection; thus, the performance and stability of the ADDC is very important. To ensure extensive testing of the ADDC, a field-programmable gate array (FPGA) mezzanine card (FMC)-based testing platform and a specially designed firmware/software are developed. This test platform works with the commercial Xilinx VC707 FPGA development kit; independent of the other electronics in the NSW, it can test all the functions of the ADDC and it has long-term stability. This article will introduce the design, testing procedure, and results of the ADDC and the FMC testing platform.