Abstract
A front-end application specific integrated circuit (ASIC) with high rate capability and deep memory buffer is needed for the silicon-strip detector for the J-PARC muon g−2/EDM experiment. In this experiment, we reconstruct a positron track from muon decay by the silicon-strip detector and measure the muon anomalous magnetic moment and the electric dipole moment precisely to explore new physics beyond the Standard Model. The front-end ASIC is required to tolerate hit rates of 1.4 MHz per strip, to be stable to the change of hit rate by a factor of 150 from the beginning to the end of the measurement, and to have deep memory for the period of 40μs with 5 ns time resolution. To satisfy the experimental requirements, we designed a prototype ASIC “SliT128B” with the Silterra 180 nm CMOS technology. We report on the design and the performance of the SliT128B.
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