Fringing-induced Barrier Lowering Research Articles

(Invited, Digital Presentation) Heterogeneous Integration of Ultrahigh-Κ Single-Crystalline SrTiO3 Membranes for Two-Dimensional Electronics

Even though competitive 2D field-effect transistors (FETs) with the scaled channel dimensions have been demonstrated, it still is a challenge to integrate 2D semiconductors and high-κ dielectrics without deteriorating their interfaces, while decreasing capacitance equivalent thickness (CET) of dielectrics to maintain the gate controllability. In particular, the dielectric/channel interface is one of the predominant factors to affect device performance, including carrier mobility, switching behavior, and drifts of device parameters. This is often caused by the nature of dielectrics used, and the integrating methodologies applied.Typically, high-κ dielectrics used in silicon technology (i.e., Al2O3 and HfO2) are inherited by 2D FETs. The amorphous nature of these oxides makes the elimination of charge scattering and trapping sites at the dielectric/channel interfaces extremely difficult, not to mention that the direct deposition of dielectrics usually damages the 2D channel and results in poor uniformity in sheer thickness. Some interfacial passivation layers and processes have been developed, but they lead to thickening overall CET instead. Alternative approaches with the crystalline dielectric materials such as multilayer hBN and epitaxial calcium fluoride (CaF2), whose surfaces are well-constructed and atomic-flat, have demonstrated the competitive advantages of crystalline dielectric over the conventional amorphous oxides in spite of relatively lower κ values.Here, we demonstrate ultra-scaled 2D FETs with desirable sub-1 nm CET through heterogeneous integration of monolayer CVD MoS2 and quasi-2D single-crystalline SrTiO3 membranes, where the optimized SrTiO3 gate dielectrics exhibit a low gate leakage (J leak < 10-2 A/cm2 at 2.5 MV/cm). Typical transistors manifest good reliability and competitive performance characteristics, including steep subthreshold swings (SS) down to ~70 mV dec-1 and ON/OFF current ratios up to 107, matching low-power specifications suggested by the latest International Roadmap for Devices and Systems (IRDS). In addition, the van der Waals (vdW) interface between quasi-2D dielectrics and 2D semiconductors moderates the unfavorable fringing-induced barrier lowering (FIBL) effect occurring in ultra-scaled Si transistors with very high-κ dielectrics, which broadens the dielectric selection in 2D electronics for future technology node.

Exploiting Fringing Fields Created by High-κGate Insulators to Enhance the Performance of Ultrascaled 2-D-Material-Based Transistors

High- κ insulators have allowed MOSFETs to obtain extremely high gate capacitances while still suppressing gate leakage. However, using high- κ gate insulators increases the strength of lateral fringing fields throughout MOSFETs, thus causing fringe-induced barrier lowering (FIBL), an electrostatic short-channel effect. The use of high- κ insulators in place of thin low- κ insulators with the same equivalent oxide thicknesses (EOTs) has, therefore, been associated with a tradeoff between a device's electrostatic control and gate leakage. In this study, we use nonequilibrium Green's function (NEGF) simulations to demonstrate that FIBL can be exploited to improve the performance of ultrascaled 2-D-material-based MOSFETs by reducing the impact of source-to-drain tunneling currents that are pervasive in extremely scaled MOSFETs, especially at low currents. As a result, we find that MOSFETs with high- κ gate insulators offer improved performances for low-power applications compared to MOSFETs with low- κ gate insulators at identical EOTs, even before considering the effect of gate leakage.

Analytical Modeling of Gate-Stack DG-MOSFET in Subthreshold Regime by Green’s Function Approach

An accurate analytical model of the gate-stack symmetric double-gate (DG) MOSFET using Green's function approach is developed in this brief. An exact analytical solution to 2-D Poisson's equation is derived in the subthreshold regime of operation, considering 2-D mixed boundary conditions and multizone techniques. It is observed that the Green's function approach of solving 2-D Poisson's equation in both oxides (t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox1</sub> and t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox2</sub> ) and silicon region can accurately predict channel potential and subthreshold current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sub</sub> ) of gate-stack DG-MOSFET. We further extend our model to mitigate the fringe-induced barrier lowering (FIBL) effect in the gate-stack device, by optimizing the interfacial layer thickness. It is observed that selection of interfacial SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer as ~0.75 times of equivalent oxide thickness is necessary to completely mitigate the FIB' effect of SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based gate-stack DG-MOSFET.

Subthreshold characteristics analysis and modeling of fully depleted silicon-on-insulator MOSFETs with high-k SiO2 stacked gate structure

In this paper, a high-k stacked and SiO2 gate structure is proposed for the fully depleted silicon-on-insulator (FDSOI) MOSFET. We constructed a two-dimensional (2D) model to compute its subthreshold surface potential, threshold voltage, drain-induced barrier lowering (DIBL) effect and fringing-induced barrier lowering (FIBL) effect. Given the structure and wide range of dielectric permittivities of a FDSOI MOSFET, the device in the subthreshold mode is separated into four distinct rectangular equivalent sources, 2D boundary value problems of the Poisson and Laplace equation are built on the polygon region. We used the eigenfunction expansion to solve the 2D boundary value problems and obtain their semianalytical solutions. The computational outcomes demonstrate that the high-k and SiO2 stacked gate structure can suppress the degradation of the FDSOI MOSFET threshold voltage and the aggravation of the DIBL effect. The computational cost of this model is much lesser than traditional models; thus, it can be used for circuit simulators and modeling of FDSOI MOSFETs.

Effect of FIBL in-conjunction with channel parameters on analog and RF FOM of FinFET

In this paper, the effect of fringe induced barrier lowering (FIBL) in-conjunction with channel parameters that includes channel thickness (TSi), channel length (Lg) and lateral straggle (σL) on analog and RF performance of FinFET, have been studied using TCAD mixed-mode Sentaurus device simulator. We focused on the variation in analog (intrinsic dc gain) and RF (cut-off frequency) figure of merit (FOM) of high-K gate dielectric based FinFET with respect to channel parameters. It is observed that the variation in intrinsic dc gain (ΔAV) aggravates with TSi scaling. We also observe a mixed response to the ΔAV with respect to variation in Lg and σL, where ΔAV follows an inverse parabolic behavior peaking at an intermediate value of Lg and σL. Variation in cut-off frequency (ΔfT) on the other hand, is negligible (slightly increases with TSi and decreases with Lg and σL). These properties of channel parameters can be handy in designing of high-K gate dielectric based FinFET for analog circuits.

Enhancing Low Temperature Analog Performance of Underlap FinFET at Scaled Gate Lengths

Higher mobility and smaller subthreshold slope are some attractive features of low-temperature operation of FinFETs at scaled gate lengths. However, very little effort has been made to enhance the analog performance of the device at lower gate lengths. In this paper, we have studied the low temperature analog performance of underlap FinFET at 16-nm gate length. We have observed that for low-temperature analog operation, high-k gate dielectric is not a viable option at this gate length, as the intrinsic dc gain (A V0 ) decreases with increase in dielectric constant of the gate dielectric because of a pronounced increase in fringe-induced barrier lowering. On the other hand, dual-k spacer-based underlap FinFET is a promising candidate in improving critical analog figures of merit (FOM), such as intrinsic dc gain (A V0 ), cutoff frequency (f T ), and maximum oscillation frequency (f max ) as the temperature is reduced. More so, the percentage increase in FOM of dual-k FinFET is enhanced at lower temperature as well as at lower gate length. Therefore, dual-k spacer underlap FinFET can be a possible solution for further device scaling at low-temperature environment.

Gate-on-germanium source tunnel field-effect transistor enabling sub-0.5-V operation

In this paper, a novel device structure for a gate-on-germanium source (GoGeS) tunnel field-effect transistor (TFET) on a bulk silicon substrate is proposed for sub-0.5-V operation. Tunneling in line with the gate electric field, which increases the effective tunneling area and, hence, the ON-state current (ION) is achieved in this device by constructing its gate on the germanium source region. To improve the subthreshold swing (SS), lateral carrier tunneling is eliminated by carefully designing the device structure. The use of a small gate-to-channel overlap results in reduced fringing-induced barrier lowering at the gate edge that further improves the SS and ION of the device. The spreading of the fringing electric field is also reduced by employing a step in the silicon channel region, which again improves both SS and ION. As a result of all these, supersteep SS and high ION are achieved, enabling sub-0.5-V operation of the proposed GoGeS TFET.

The impact of high-k gate dielectric and FIBL on performance of nano DG-MOSFETs with underlapped source/drain regions

The impact of high-k gate dielectrics and fringing induced barrier lowering (FIBL) effects on a nano double gate MOSFET is studied over a wide range of dielectric permittivity using ballistic quantum simulation. The simulations are based on self-consistent solution of 2D Poisson equation and Schrodinger equation with open boundary conditions, within the Non-equilibrium Green's Function formalism. The numerical results show that the use of high-k gate at fixed equivalent oxide thickness (EOT), deteriorates the short channel effects due to FIBL effect. We show that the FIBL can be effectively suppressed by using underlapped source/drain region.

Analysis of Off-State Leakage Current Characteristics and Mechanisms of Nanoscale MOSFETs with a High-k Gate Dielectric

The off-state leakage current characteristics of nanoscale channel metal-oxide-semiconductor field-effect transistors with a high-k gate dielectric are thoroughly investigated. The off-state leakage current can be divided into three components: the gate leakage current, the source leakage current, and the substrate leakage current. The influences of the fringing-induced barrier lowering effect and the drain-induced barrier lowering effect on each component are investigated separately. For nanoscale devices with high-k gates, the source leakage current becomes the major component of the off-state leakage current.

The influence and explanation of fringing-induced barrier lowering on sub-100 nm MOSFETs with high-k gate dielectrics

The fringing-induced barrier lowering (FIBL) effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator. An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect. The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance. Based on equivalent capacitance theory, the influences of channel length, junction depth, gate/lightly doped drain (LDD) overlap length, spacer material and spacer width on FIBL is thoroughly investigated. A stack gate dielectric is presented to suppress the FIBL effect.

A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

We investigate the influence of voltage drop across the lightly doped drain (LDD) region and the built-in potential on MOSFETs, and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson's equation in the silicon and gate dielectric layers. The model can predict the fringing-induced barrier lowering effect and the short channel effect. It is also valid for non-LDD MOSFETs. Based on this model, the relationship between threshold voltage roll-off and three parameters, channel length, drain voltage and gate dielectric permittivity, is investigated. Compared with the non-LDD MOSFET, the LDD MOSFET depends slightly on channel length, drain voltage, and gate dielectric permittivity. The model is verified at the end of the paper.

Analytical model including the fringing-induced barrier lowering effect for a dual-material surrounding-gate MOSFET with a high-κ gate dielectric

By solving Poisson's equation in both semiconductor and gate insulator regions in the cylindrical coordinates, an analytical model for a dual-material surrounding-gate (DMSG) metal—oxide semiconductor field-effect transistor (MOSFET) with a high-κ gate dielectric has been developed. Using the derived model, the influences of fringing-induced barrier lowering (FIBL) on surface potential, subthreshold current, DIBL, and subthreshold swing are investigated. It is found that for the same equivalent oxide thickness, the gate insulator with high-κ dielectric degrades the short-channel performance of the DMSG MOSFET. The accuracy of the analytical model is verified by the good agreement of its results with that obtained from the ISE three-dimensional numerical device simulator.

Fringe-induced barrier lowering (FIBL) included sub-threshold swing model for double-gate MOSFETs

A physical, compact, short-channel sub-threshold swing model for undoped-gate MOSFETs has been developed to include the fringe-induced barrier lowering effect associated with high-permittivity (high-κ) gate dielectrics. Using this new device model, we found that the degradation becomes worse when the channel length becomes shorter and both the off-state current (Ioff) and sub-threshold slope(s) rollup when κ is increased. It is indicated that a way to keep a reasonable channel length/vertical physical thickness ratio could be to suppress the FIBL effect in nanoscale DG MOSFET. The result showed that the analytical model was in agreement with the published numerical simulation over a wide range of device parameters.

The impact of high-k dielectrics on the performance of Schottky barrier source/drain (SBSD) ultra-thin body (UTB) SOI MOSFET

The impact of high-k dielectrics on the performance of Schottky barrier source/drain (SBSD) ultra-thin body (UTB) SOI is investigated in this paper. With the dielectric constants increasing, the on-state currents of SBSD UTB SOI MOSFET decrease, which suggests that the fringing induced barrier lowering (FIBL) is not the major mechanism for the variation of Schottky barrier height. This phenomenon can be understood in terms of the fringing induced barrier shielding (FIBS). It is also shown that the influence of high-k dielectrics on the performance is quite different in the cases that source/drain and gate electrode have an offset or overlap. For the device with an overlap， the structure with a low-k interfacial layer between high-k gate dielectric and substrate is quite effective in suppressing the degradation of drive current due to FIBS. However, for the device with an offset, the combination of high-k dielectric spacer with stack gate can significantly improve the on-state current. This fact can be explained in terms of the refraction of lines of electric force from gate electrode at interfaces of two materials with different dielectric constants. These lines of electric force with refraction can concentrate at the source region, thus lowering the barrier heights and improving the drive currents. Besides, it is shown that on-state current has a local maximum in the case that source/drain and gate electrode has an offset. The structure parameters can be optimized to improve the drive current.

Gate Fringe-Induced Barrier Lowering in Underlap FinFET Structures and Its Optimization

The difficulty to fabricate and control precisely defined doping profiles in the source/drain underlap regions of FinFETs necessitates the use of undoped gate underlap regions as the technology scales down. We present a phenomenon called the gate fringe-induced barrier lowering (GFIBL) in FinFETs with undoped underlap regions. In these FinFETs, we show that the GFIBL can be effectively used to improve Ion. We propose the use of high-kappa spacers in such FinFETs to enhance the effect of GFIBL and thereby achieve better device and circuit performance. When compared with the underlap FinFETs with Si3N4 spacers, with kappa=20 spacers, we show that it is possible to achieve an 80% increase in Ion at iso-Ioff conditions and a 15% decrease in the inverter delay for a fan-out of four.

Fringing Electric Field Effect on 65-nm-Node Fully Depleted Silicon-on-Insulator Devices

In this study, the fringing electric field effect on 65-nm-node technology fully depleted silicon-on-insulator (FD SOI) device is comprehensively examined. A new anomalous degradation in device on-state/off-state characteristics on a nanoscale metal–oxide–semiconductor field-effect transistor (MOSFET) with high-κ gate dielectrics is reported, the so-called fringing-induced barrier lowering (FIBL). This is due to the decrease in fringing electric field and increase in the gate dielectric thickness when gate dielectric permittivity increased. We observe that FIBL can be effectively suppressed using a stack gate dielectric structure. In addition, we also implement a high-κ offset spacer to further improve the on-state driving current Ion to approximately 26% higher than that of a conventional silicon dioxide offset spacer and reduce the off-state leakage current Ioff by about 34%. This benefit is due to the enhanced high vertical channel electric field obtained via the offset spacer using a high-κ material as a spacer. This enhanced fringing electric field can markedly increase Ion/Ioff current ratio and reduce subthreshold swing (S-factor) to improve MOSFET performance, which implies that gate-to-channel controllability can be improved markedly. This would play an important role beyond the 65-nm-node technology.

Quantum short-channel compact model for the threshold voltage in double-gate MOSFETs with high-permittivitty gate dielectrics

An analytical model of the threshold voltage for long channel double-gate metal-oxide-semiconductor field effect transistor is developed, applicable to both symmetric and asymmetric structures with thin films (<10 nm) and high-permittivity gate dielectrics (with permittivities > 10). The model takes into account short-channel effects, carrier quantization and fringing-field induced barrier lowering induced by the high-permittivity gate layer. The model assumes a parabolic dependence of the potential with position in the silicon film at threshold, enabling the development of an analytical expression for the surface potential. Compared to previous models only derived for undoped films, the present approach considers both mobile charge and depleted charge terms in Poisson’s equation. The model is fully validated by numerical simulation and is used to predict the impact of the fringing-induced barrier lowering on the threshold voltage of double-gate devices as a function of the gate stack composition and the device gate length.

A simulation analysis of FIBL in decananometer Double-Gate MOSFETs with high- κ gate dielectrics

In this work, the degradation of electrical performances of Double-Gate MOSFET due to the fringing induced barrier lowering (FIBL) effect induced by high- κ gate dielectrics is investigated using a two-dimensional quantum-mechanical simulation code. Our numerical results show that all electrical parameters, such as the threshold voltage ( V T), device immunity to short-channel effects, off-state current ( I off), and subthreshold slope (S) are degraded when κ increases (3.9 < κ < 100). This degradation is both function of the channel length and the gate dielectric stack composition (number of layers, κ value). In particular, it is shown that the introduction of a thin (<1 nm thick) interfacial oxide layer can reduce or even completely suppress the FIBL for a given equivalent oxide thickness of the gate dielectric stack.

Fringe-induced barrier lowering (FIBL) included threshold voltage model for double-gate MOSFETs

A physical, compact, short-channel threshold voltage model for undoped double-gate MOSFETs has been extended through a phenomenological approach to include the fringe-induced barrier lowering (FIBL) effect associated with high-permittivity (high- k) gate dielectrics. The resulting analytical model closely describes published numerical simulations over a wide range of device/material parameters. Exploiting the new device model, a concerted analysis combining FIBL-enhanced short-channel effects and gate direct tunneling current is performed on candidate high- k gate dielectrics to assess their overall impact on DG MOSFET scaling. It is projected that high- k gate dielectrics may extend DG MOSFET scaling beyond that with SiO 2 by 10–20% for a 2–3× smaller equivalent oxide thickness of high- k dielectrics than that of SiO 2.

A Comprehensive Study on the FIBL of Nanoscale MOSFETs

Fringing-induced barrier lowering (FIBL) effect on nanoscale MOSFET is comprehensively examined. It is observed that by combining stack gate dielectric, conductive spacer, short sidewall spacer, and minimum gate/drain (G/D) overlap, the I/sub off/ with a dielectric constant of (k) 100 is only 1.6 times higher than that with k=3.9 when the gate length is 25 nm. The fully depleted silicon-on-insulator device shows even better FIBL immunity. It is concluded that although the FIBL effect can not be eliminated, it would not an issue beyond the 45-nm technology node.