The impact of high-k gate dielectric and FIBL on performance of nano DG-MOSFETs with underlapped source/drain regions

Abstract

The impact of high-k gate dielectrics and fringing induced barrier lowering (FIBL) effects on a nano double gate MOSFET is studied over a wide range of dielectric permittivity using ballistic quantum simulation. The simulations are based on self-consistent solution of 2D Poisson equation and Schrodinger equation with open boundary conditions, within the Non-equilibrium Green's Function formalism. The numerical results show that the use of high-k gate at fixed equivalent oxide thickness (EOT), deteriorates the short channel effects due to FIBL effect. We show that the FIBL can be effectively suppressed by using underlapped source/drain region.