Design Of Frequency Synthesizer Research Articles

A tool for power and phase noise optimization in frequency synthesizers

In this paper, we present a CAD technique to design low-power and low phase noise integrated frequency synthesizers. This technique introduces a key parameter, Phase Noise per Unit Power, which correlates phase noise and power among all the sub-circuits in the frequency synthesizer. By correlating the performance of all the independent circuits together, sophisticated synthesizer design and optimization can be significantly simplified. We demonstrate a 1.8 GHz frequency synthesizer design in a 0.18 μm CMOS process achieving ?132 dBc/Hz phase noise at 100 kHz offset with less than 4.3 mW power consumption.

Design of frequency synthesizer based on DDS+PLL

Design of frequency synthesizer based on DDS+PLL

A BiCMOS Dual-Band Millimeter-Wave Frequency Synthesizer for Automotive Radars

Design and implementation of a millimeter-wave dual-band frequency synthesizer, operating in the 24 GHz and 77 GHz bands, are presented. All circuits except the voltage controlled oscillators are shared between the two bands. A multi-functional injection-locked circuit is used after the oscillators to simplify the reconfiguration of the division ratio inside the phase-locked loop. The 1 mm times 0.8 mm synthesizer chip is fabricated in a 0.18 mum silicon-germanium BiCMOS technology, featuring 0.15 mum emitter-width heterojunction bipolar transistors. Measurements of the prototype demonstrate a locking range of 23.8-26.95 GHz/75.67-78.5 GHz in the 24/77 GHz modes, with a low power consumption of 50/75 mW from a 2.5 V supply. The closed-loop phase noise at 1 MHz offset from the carrier is less than -100 dBc/Hz in both bands. The frequency synthesizer is suitable for integration in direct-conversion transceivers for K/W-band automotive radars and heterodyne receivers for 94 GHz imaging applications.

Diophantine Frequency Synthesizer Design for Timekeeping Systems

Diophantine Frequency Synthesis (DFS), a number‐theoretic approach to the design of very high resolution frequency synthesizers, was introduced in 2006. Further work concerning the impact of controlling mixing products for high‐spectral purity was addressed and reported at the 2007 European Frequency and Time Forum. The focus of this paper is on the implementation of nested DFS architectures targeting microphase‐type applications for precision timekeeping systems. We have shown that DFS does not impart any extraordinary design constraints on spectral purity in comparison to commonly used high resolution frequency synthesis techniques such as DDS or fractional N. Here we describe a design approach for 10 MHz synthesizers with 1E‐13 fractional resolution in consecutive steps ranging ±10 Hz. The synthesizers generate their output from a 10 MHz reference standard. Such synthesizers are essential to accomplishing precision frequency correction in timekeeping systems.

Fully integrated frequency synthesizer design for wireless network application with digital programmability

AbstractA 2.60‐GHz integer‐N frequency synthesizer was designed and implemented in SiGe BiCMOS technology. The single chip includes fully integrated VCO (voltage control oscillator) as well as LPF (loop‐filter). The synthesizer provides a wide frequency range of 300 MHz, which covers 2.59–2.66 and 2.8725–2.9025 GHz, with a single VCO. Digital technique is employed at VCO and charge‐pump to cover the frequency range and cater for process variation. Using reference frequency of 2.5 MHz, the fabricated prototype demonstrates a settling time of 32 μs, and reference spur below −56 dBc. The synthesizer's phase noise is −115 dBc/Hz at 1.0‐MHz offset frequency. It consumes approximately 42 mW power from a 3.0 V single supply, with a total active area of 2.34 mm2. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 2579–2582, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22773

A low phase noise design for ultrawideband frequency synthesizer

AbstractA low phase‐noise frequency synthesizer design for ultrawideband is demonstrated in a 0.18‐μm CMOS process. It combines a low phase‐noise voltage‐controlled oscillator with two‐stage dividers and a switched buffer multiplexer with low layout complexity. Because of the symmetrical independent architecture of this switch buffer design, it can reduce the additional phase noise created by the traditional multiplexer stage. Here, this low phase noise design in three LO bands (8448, 4224, and 2112 MHz) is demonstrated. The measurement shows that in these three LO band, this new structure can achieve phase noise of less than −121 dBc/Hz at 1 MHz offset. The frequency tuning range is 10% while consuming only 52.2 mW from a 1.8‐V supply. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 1159–1162, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22384

The Design and Analysis of a DLL-Based Frequency Synthesizer for UWB Application

A delay-locked loop (DLL)-based frequency synthesizer is designed for the ultrawideband (UWB) Mode-1 system. This frequency synthesizer with 528-MHz input reference frequency achieves less than 9.5-ns settling time by utilizing wide loop bandwidth and fast-settling architecture. Additionally, a discrete-time model of the DLL and an analytical model of phase noise of the delay line are proposed in this work. Experimental results show great consistency with predicted settling time and phase noise. The circuit has been fabricated in a 0.18-/spl mu/m CMOS technology and consumes only 54 mW from a 1.8-V supply. It exhibits a sideband magnitude of -35.4 dBc and -120-dBc/Hz phase noise at the frequency offset of 1 MHz.

Award winning student paper: Design and implementation of a fractional-n frequency synthesizer for cellular systems

Frequency synthesis presents one of the most challenging subsystems in a monolithic transceiver implementation. This paper presents a PLL (phase-locked loop) frequency synthesizer based on fractional-N frequency synthesis techniques, employing direct charge injection for Fractional spurious tone reduction and an integrated VCO (voltage-controlled oscillator) with an active inductor resonant tank. A 0.35 μm CMOS process is used for implementation.

FULLY INTEGRATED FREQUENCY SYNTHESIZERS: A TUTORIAL

Frequency synthesizer is a key building block of fully-integrated wireless communications systems. Design of a frequency synthesizer (FS) requires the understanding of not only the circuit-level but also of the transceiver system-level considerations. The FS design challenge involves strong trade-offs, and often conflicting requirements. In this tutorial, the general implementation issues and recent developments of frequency synthesizer design are discussed. Simplified design approach should provide readers with sufficient intuition for fast design and troubleshooting capability. Open problems in this FS field are briefly discussed.

Novel approach to the design of direct digital frequency synthesizers based on linear interpolation

This paper presents a novel approach to the design of direct digital frequency synthesizers (DDFSs) with phase-to-sinusoid amplitude conversion blocks based on linear interpolation. For such DDFSs, the first quadrant of the sine function is approximated with a number of linear segments. Simple control circuitry reconstructs a full sine wave by symmetry. DDFS architectures using linear interpolation are first discussed, and an analysis of their spectral properties is given. From this analysis, an upper bound is provided for the spurious free dynamic range (SFDR) that can be attained for a given number of linear segments. A detailed and systematic procedure for the selection of linear segment coefficients achieving a desired SFDR is then proposed. A generalized multiplierless linear interpolation DDFS architecture is described, and specific designs achieving 84 and 96 dBc of SFDR are discussed and compared with previous work. It is shown that the complexity of synthesizers based on the new approach, in terms of the number of transistors and silicon area, is significantly less than that of previously presented DDFS designs of similar performance.

Design of a wide-band frequency synthesizer based on TDC and DVC techniques

A wide-band frequency synthesizer based on time-to-digital (TDC) and digital-to-voltage (DVC) conversion techniques is proposed here. The proposed frequency synthesizer has the capabilities of jitter reduction and large bandwidth, making it more robust for high-frequency applications. A test chip is designed and fabricated in 0.6-/spl mu/m CMOS single-poly triple-metal process. Here, the novel DVC circuit is realized by tristate inverters, where the resolution can achieve 0.2 mV. Control stability of jitter can improve about 24 dB by exploiting the TDC-based controller. In order to achieve high output frequency and large output range, an analog voltage-controlled oscillator is designed to provide a locked range from 900 to 1900 MHz with <22 kHz resolution at 3.3 V. Simulation and test results show that the proposal can work as expected. Moreover, the TDC-based controller can be treated as soft IP to speed up turnaround time.

Design of DDFS-driven PLL frequency synthesizer with reduced complexity

DDFS-driven PLL synthesizer has a high frequency resolution and wide frequency bandwidth. Since the output of DDFS is a synthesized analog signal, a waveform shaper is needed to provide the digital input for a DDFS-driven PLL synthesizer using the digital type phase detector. Furthermore, a lot of components in a DDFS unit can increase the switching time and the power consumption. In this paper, we propose a new design method of a DDFS-driven PLL synthesizer, which does not need the waveform shaper as well as the extra circuits of DDFS. As a result, the proposed method makes improvements to such quality factors as switching time and power consumption, compared with the conventional DDFS-driven PLL frequency synthesizer.

Models for systematic design and verification of frequency synthesizers

Recently, much effort has been put on the integration of telecommunication front-ends. For a semiconductor company to follow the large market request in shortening the time-to-market constraint for new products, a systematic design methodology has to be followed, starting from a top-down design followed by a bottom-up verification. This paper provides, in models, each of these design phases for the example of frequency synthesizers. During the design phase, fast models are needed to explore the design space. On the other hand, accurate nonlinear models are derived for the verification phase to simulate complex specifications, e.g., the oscillator's output phase noise. An illustration of these models is based on the design of a 1.8 GHz CMOS frequency synthesizer.

A fully integrated low-noise 1-GHz frequency synthesizer design for mobile communication application

This paper describes a fully monolithic phase-locked loop (PLL) frequency synthesizer circuit implemented in a standard 0.8-/spl mu/m CMOS technology. To be immune to noise, all the circuits in the synthesizer use differential schemes with the digital parts designed by static logic. The experimental voltage controlled oscillator (VCO) has a center frequency of 800 MHz and a tuning range of /spl plusmn/25%. The measured frequency synthesizer performance has a frequency range from 700 MHz to 1 GHz with -80 dBc/Hz phase noise at a 100 kHz carrier offset. With an active area of 0.34 mm/sup 2/, the test chip consumes 125 mW at maximum frequency from a 5 V supply. The only external components are the supply decoupling capacitors and a passive filter.

Low-noise voltage-controlled oscillators using enhanced LC-tanks

Frequency synthesizers used in modern telecommunication systems, such as cellular telephones, need to have very low phase noise. Therefore, in the design of high performance frequency synthesizers using Phase Locked Loops (PLL), the Voltage-Controlled Oscillator (VCO) has become a key issue. The trend towards monolithic Integration poses some major challenges. This paper discusses the phase noise aspects of LC-tuned oscillators. A general formula is developed, based on the concepts of effective resistance and capacitance. The formula also applies for oscillators using active inductors. From these results the importance of an inductor with very low series resistance is apparent. To circumvent the technological limits given by an Inductor's series resistance, a presented enhanced LC-tank can be used to make a trade-off between noise and power.

A new phase-locked loop used in a frequency synthesizer

A well-known contradiction in phase-locked frequency synthesizer design is between frequency resolution, on the one hand, and bandwidth of the phase-locked loop (PLL), on the other. To solve this problem, a technique that uses an algorithm that produces a group of different divide numbers to the programmable feedback frequency divider of PLL for each required output frequency is presented. The interference frequency at the output of the phase detector of PLL and the frequency resolution can then be set independent of each other. High resolution and wide bandwidth are achieved simultaneously, with a simple synthesizer design leading to savings in power consumed and device cost.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Analysis of Digitally Generated Sinusoids with Application to A/D and D/A Converter Testing

Several aspects of the design of digital frequency synthesizers are considered, and a detailed analysis of the spectral purity of digitally synthesized frequencies is given. These results are then applied to a specific application: the testing of A/D and D/A converters.

Design of an Indirect Frequency Synthesizer Using Second-Order Type-Two Loop

In this paper, a new design procedure for finding the optimum loop-bandwidth for an indirect synthesizer, based on the experimental study of the synthesized signal is described. It is illustrated for a frequency range of 12 MHz to 13.5 MHz in 2.5 kHz steps. Nevertheless, the procedure is applicable to the design of indirect synthesizers in any frequency range.

A circuit approach to SAW filterbanks for frequency synthesis

A SAW filterbank (2.5 × 0.9 cm) coupled to a miniature silicon-on-sapphire (SOS) p-i-n diode, multiple-input single-output RF switch array (2.5 × 0.25 cm) forms the basis of a very compact UHF frequency synthesizer. In this paper the operation, design, fabrication, and performance of rapid-switching SAW frequency synthesizers is described. Experimental measurements depicting the spectral purity of the waveforms synthesized by two devices; one fabricated on LiTaO 3 and the other on AlN-on-sapphire, operating over respective frequency ranges of 520-650 MHz and 970-1210 MHz are provided.

The problem of frequency synthesis

Frequency synthesis employs precise frequency standards to obtain by means of a frequency conversion process many output frequencies from the one accurate source, each of which can be individually selected. The output frequencies are multiples of harmonic fractions of the frequency standard.The paper reviews the basic techniques of addition or subtraction and division employed and analyses some of the present frequency synthesizer designs.