A fully integrated low-noise 1-GHz frequency synthesizer design for mobile communication application

Abstract

This paper describes a fully monolithic phase-locked loop (PLL) frequency synthesizer circuit implemented in a standard 0.8-/spl mu/m CMOS technology. To be immune to noise, all the circuits in the synthesizer use differential schemes with the digital parts designed by static logic. The experimental voltage controlled oscillator (VCO) has a center frequency of 800 MHz and a tuning range of /spl plusmn/25%. The measured frequency synthesizer performance has a frequency range from 700 MHz to 1 GHz with -80 dBc/Hz phase noise at a 100 kHz carrier offset. With an active area of 0.34 mm/sup 2/, the test chip consumes 125 mW at maximum frequency from a 5 V supply. The only external components are the supply decoupling capacitors and a passive filter.