Design Of Frequency Synthesizer Research Articles

Design of a ROM-Less Direct Digital Frequency Synthesizer on FPGA

Design of a ROM-Less Direct Digital Frequency Synthesizer on FPGA

Design and Implementation of Pll Frequency Synthesizer using PE3336 IC for IRS Applications

The design and experimental verification of a low phase noise phase locked loop (PLL) frequency synthesizer using Peregrine’s PE83336 IC is presented. This PLL is used as frequency synthesizer which generates stable and low phase noise signal for space applications. A stable reference frequency of 22.8MHz is provided to the PLL through a temperature compensated crystal oscillator (TCXO). Experimental results of the PLL frequency synthesizer shows the excellent performance achieved at Xband. The PLL model implemented with frequency resolution of 5.8MHz, and phase noise better than 81dBc/Hz @ 1 kHz offset at X-band. The complete model is fabricated on RT-duroid 6010 substrate.

An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs

Digital fractional-N phase-locked loops (PLLs) are an attractive alternative to analog PLLs in the design of frequency synthesizers for wireless applications. However, the main obstacle to their full acceptance in the wireless-systems arena is their higher content of output spurious tones, whose level is ultimately set by the nonlinearity of the time-to-digital converter (TDC). The known methods to improve the linearity of the TDC either increase its dissipation and phase noise or require slow foreground calibrations. By contrast, the class of digital PLLs based on a one-bit TDC driven by a multibit digital-to-time converter (DTC) substantially reduces power dissipation and eliminates the TDC nonlinearity issues. Although its spur performance depends on DTC linearity, the modified architecture enables the application of a background adaptive pre-distortion which does not compromise the PLL phase-noise level and power consumption and is much faster than other calibration techniques. This paper presents a 3.6-GHz digital PLL in 65-nm CMOS, with in-band fractional spurs dropping from -39 to -52 dBc when the pre-distortion is enabled, in-band phase noise of -103 dBc/Hz and power consumption of 4.2 mW.

Design of Dual High Precision High Resolution Frequency Synthesizer Based on AD9854

To obtain dual high-precision and high-resolution numerical control signal source, and accurately adjust the signal frequency, the paper proposed a method based on AD9854 direct digital frequency synthesis technology, design and implementation the dual high-precision and high-resolution frequency synthesizer. FPGA controlled AD9854 registers to achieve frequency modulation, and after amplification processing output by THS3001, increasing the output signal drive capability. Comprehensive consideration the anti-jamming measures, the system is stable and reliable, the output signal frequency range from 500Hz to 30MHz relative error is less than 10ppm, and can numerical adjust the sine and square wave frequency and has a sweep output mode. Compared with previous equipment, it reduces the system power consumption and volume.

The Delta-Sigma Modulator of Fractional-N Frequency Synthesizer for Wireless Sensors Network Applications

This paper presents a design of fractional-N frequency synthesizer with low dithering, which is fabricated in a 130nm CMOS process. A 3rd-order delta-sigma modulator is based on digital multi-stage noise shaping (MASH) structure with its second and third stage dithered by 7-bit linear feedback shift register (LFSR) was designed for the frequency synthesizer, and a long word is used for the first modulator in the MASH structure. The simulation result of the whole frequency synthesizer shows that it can output two-way I/Q signal between 2.28GHz and 2.53GHz, and its spurs are lower than-75dBc.

Hardware implementation of 32-bit high-speed direct digital frequency synthesizer.

The design and implementation of a high-speed direct digital frequency synthesizer are presented. A modified Brent-Kung parallel adder is combined with pipelining technique to improve the speed of the system. A gated clock technique is proposed to reduce the number of registers in the phase accumulator design. The quarter wave symmetry technique is used to store only one quarter of the sine wave. The ROM lookup table (LUT) is partitioned into three 4-bit sub-ROMs based on angular decomposition technique and trigonometric identity. Exploiting the advantages of sine-cosine symmetrical attributes together with XOR logic gates, one sub-ROM block can be removed from the design. These techniques, compressed the ROM into 368 bits. The ROM compressed ratio is 534.2 : 1, with only two adders, two multipliers, and XOR-gates with high frequency resolution of 0.029 Hz. These techniques make the direct digital frequency synthesizer an attractive candidate for wireless communication applications.

Design of Frequency Synthesizer Based on DDS + PLL Technology

This paper presents a design plan for the frequency synthesizer base on DDS and PLL of the digital receiver, the main hardware selection is shown. Finally through the system test, the results show that the frequency accuracy of the frequency synthesizer reaches 3.72×10-8, the resolution is 1Hz, the phase noise is 103dBc/Hz@1 kHz the clutter rejection is 67dB and the frequency conversion time reaches 9.6ms. This frequency synthesizer can produce low phase noise, high resolution and high stability of the broadband signal. It has excellent technical performance, has been widely used in engineering.

A CMOS 77-GHz Receiver Front-End for Automotive Radar

This paper presents the design of a receiver (Rx) front-end for automotive radar application operating at 76-77 GHz. The Rx employs a double conversion architecture, which consists of a five-stage low-noise amplifier (LNA), a sub-harmonic mixer (SHM), and a double-balanced passive mixer (PSM). By adopting this architecture, millimeter-wave frequency synthesizer design can be relaxed. In the LNA layout, the output of each stage is positioned close to the input of the follow stage, thus creating a LC resonance load. As a result, complex interstage matching networks is simplified. The SHM driven by a 38-GHz local oscillator (LO) is adopted to avoid push/pull effect and power consumption of the voltage-controlled oscillator. A PSM is utilized for the second conversion since it consumes no dc current and has low flickering noise. To connect the singled-ended LNA and SHM, a 77-GHz balun is designed; and for driving the SHM, two 38-GHz baluns and an in-phase/quadrature coupler to provide quadrature 38-GHz LO are designed. The proposed Rx is implemented in a 65-nm CMOS technology and measurement results show 16-dB voltage gain and 13-dB calculated noise figure while dissipating 23.5 mA from a black 1.2-V supply.

A Wideband Frequency Synthesizer with High Frequency Resolution

ABSTRACTThis article presents the design and implementation of a wideband frequency synthesizer which uses a direct digital synthesis as a fractional divider in the phase‐locked loop. The frequency resolution is 7.1 × 10−5 Hz. A phase‐domain model of this synthesizer is analyzed and simulated. A formula of output phase noise is derived. The output phase noise of synthesizer is −124 dBc/Hz (10 kHz offset) at the frequency of 1 GHz. The frequency synthesizer model has been designed with advantages of wide bandwidth, low phase noise, high‐frequency resolution, low spurious, high frequency stability, and simple structure. With frequency multiplier and divider module, the frequency band of synthesizer can be extended from 250 MHz to 8 GHz. The module is suitable for communication instrument. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2454–2457, 2013

MBOA용 3~10GHz UWB 주파수합성기의 설계

UWB의 일종인 MBOA 무선통신 시스템에 내장하기 위한 광대역 RF 주파수 합성기를 0.13㎛ 실리콘 CMOS 기술을 이용하여 설계하였다. 효율적인 MBOA 클록신호 생성을 위하여 낮은 주파수를 갖는 하위 밴드에서는 큰 배수로 주파수를 합성하고, 높은 주파수를 갖는 상위 밴드에서는 작은 배수로 주파수를 합성함으로서 VCO의 발진범위를 대폭 줄일 수 있는 새로운 방법을 적용하였다. 설계된 PLL 회로는 P-MOS 코어 구조의 VCO 및 수퍼 다이나믹 구조의 주파수 분할기를 사용하여 고속 및 광대역 동작 범위를 확보하였다.

Design and development of programmable frequency synthesizer for WiMAX/WiFi wireless communication

Rapid advancements in nanotechnology are going to bring radical changes in the society and particularly in wireless communication where small, smart and speedy systems are everyone's first choice. This is possible as application of nanotechnology is taking place in WiMAX/WiFi and other wireless communication systems, which is ‘State-of-the-Art’ technology at the moment. Evolution of microelectronics towards miniaturization is one of the main motivations for nanotechnology. The continued improvements in miniaturization, speed and power reduction in information processing devices, sensors, displays, logic devices, storage devices, transmission devices, etc. will bring another technical revolution, which will change our life. In our research work, we would like to focus on design and development of programmable frequency synthesizer for WiMAX/WiFi wireless communication (to the scale of < 50 nanometer). The transceiver will support fixed, portable, and mobile WiMAX operation. The design strategies focus on maximum operating frequency, low power consumption, low voltage operation, minimize number of gates/transistors, CMOS Technology (< 50 nanometer), reduced fabrication cost, high speed applications in WiMAX/WiFi/Satellite communications, flexibility, programmability, and service efficiency. The proposed ‘Programmable frequency synthesizer will be a new device with its varied application for WiMAX/WiFi/Satellite and other wireless communication systems. The transceiver will support fixed, portable, and mobile WiMAX operation.

Direct Digital Frequency Synthesizer Simulation and Design by means of Quartus-ModelSim

Direct Digital Frequency Synthesizer Simulation and Design by means of Quartus-ModelSim

RF PLL용 26GHz 가변 정수형 주파수분할기의 설계

This paper describes design of a variable-N frequency synthesizer for RF PLL with silicon CMOS technology being used as an application of the UWB system like MBOA. To get good performance of speed and noise super dynamic circuits was used, and to get variable-N division ratio MOSFET switching circuits was used. Especially to solve narrow bandwidth problem of the dynamic circuits load resistance value of unit divider block was varied. Simulation results of the designed circuit shows very fast and wide operation characteristics as 5~26GHz frequency range.

Direct Digital Frequency Synthesizer Design and Implementation on FPGA

Direct Digital Frequency Synthesizer Design and Implementation on FPGA

Design of Multi-Mode Frequency Synthesizer for System Level Clocking

This paper describes the design of a multi-mode frequency synthesizer. The oscillation frequency of VCO is 5GHz, and the reference clock accepts 18-39MHz. A multi-mode controller which contains triangular wave generator, 3rd order Sigma-Delta modulator, programmable divider, etc, is proposed in this paper. The measurements show a less than 58dB spur, the spectrum spread about 4700ppm and the EMI is reduced about 22dB. This circuit consumes 28mW power at 1.2V power supply and is manufactured in 0.13um CMOS process.

Ultra-Stable Very-Low Phase-Noise Signal Source for Very Long Baseline Interferometry Using a Cryocooled Sapphire Oscillator

The design and implementation of a novel frequency synthesizer based on low phase-noise digital dividers and a direct digital synthesizer is presented. The synthesis produces two low noise accurate tunable signals at 10 and 100 MHz. We report the measured residual phase noise and frequency stability of the syn thesizer and estimate the total frequency stability, which can be expected from the synthesizer seeded with a signal near 11.2 GHz from an ultra-stable cryocooled sapphire oscillator (cryoCSO). The synthesizer residual single-sideband phase noise, at 1-Hz offset, on 10and 100-MHz signals was -135 and -130 dBc/Hz, respectively. The frequency stability contributions of these two sig nals was σy = 9 × 10-15 and σy = 2.2 × 10-15, respectively, at 1-s integration time. The Allan deviation of the total fractional frequency noise on the 10- and 100-MHz signals derived from the synthesizer with the cry oCSO may be estimated, respectively, as σy ≈ 3.6 × 10-15 τ-1/2 + 4 × 10-16 and σy ≈ s 5.2 × 10-2 × 10-16 τ-1/2 + 3 × 10-16, respectively, for 1 ≤ τ <; 104s. We also calculate the coherence function (a figure of merit for very long baseline interferometry in radio astronomy) for observation frequencies of 100, 230, and 345 GHz, when using the cry oCSO and a hydrogen maser. The results show that the cryoCSO offers a significant advantage at frequencies above 100 GHz.

Design and Optimization of Microwave Frequency Synthesizer Based on DDS

This paper introduces a new frequency synthesizer scheme –Nested-mixer DDS driving PLL frequency synthesizer. It is a dual loop topology. The AUX PLL uses high comparison frequency. The main PLL comparison frequency is high and changed continuously. It overcomes the shortcoming of long switching time which happens in the traditional DDS+PLL. Taking some optimized measures helps to further improve the synthesizer performance. Oversampling is used to reduce DDS output spurious level. Optimizing the circuit layout and structure, using 6 layers PCB, making control and data signal lines as a separate layer, and sandwiching it between analog ground and digital ground plane, minimize the external noise impact on the frequency synthesizer. Finally, a high performance microwave frequency synthesizer with high resolution has been achieved. It has been applied successfully to a military transmitter and a measuring receiver.

All-Digital Frequency Synthesizer Using a Flying Adder

This brief presents an all-digital frequency synthesizer based on the flying adder (FA) architecture. The FA is a fascinating architecture for frequency synthesizer designs due to its simplicity and effectiveness. The FA-based frequency synthesizer can simply use a set of multiple phase reference signals to generate a desired frequency to achieve fast frequency switching. In the proposed work, the frequency synthesizer adopts an all-digital phase-locked loop to provide a steady reference signal for the FA. The proposed frequency synthesizer is implemented in a standard 0.18-μm CMOS cell-based technology, and the core area is 0.16 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The output frequency range is 39.38-226 MHz, and the peak-to-peak jitter is less than 130 ps.

A 2-to-2.4-GHz differentially-tuned fractional-N frequency synthesizer for DVB tuner applications

This paper describes the design of a fractional-N frequency synthesizer for digital video broadcasting-terrestrial (DVB-T) receivers. Transfer functions in differentially-tuned PLL are derived and loop parameters are designed. In addition, a fully-differential charge pump is presented. An 8/9 high speed prescaler is analyzed and the design considerations for the CML logic are also presented. Test results show that the RMS phase error is less than 0.7° in integer-N mode and less than 1° in fractional-N mode. The implemented frequency synthesizer draws 10 mA from a 1.8-V supply while occupying a die area of about 1-mm2 in a 0.18-μm CMOS process.

A direct digital frequency synthesizer based on a new form of polynomial approximations

A new form of polynomial approximations of the discrete sinusoid waveform is proposed for the design of a direct digital frequency synthesizer (DDFS). With the polynomial approximation, only square circuits are needed for the DDFS realization, which will tremendously reduce the chip area, and a spurious free dynamic range (SFDR) of more than 95 dBc can be achieved. Based on the approximation, the DDFS circuit is designed and validated via simulations with the TSMC 0.18 μm cell-library.