Award winning student paper: Design and implementation of a fractional-n frequency synthesizer for cellular systems

Abstract

Frequency synthesis presents one of the most challenging subsystems in a monolithic transceiver implementation. This paper presents a PLL (phase-locked loop) frequency synthesizer based on fractional-N frequency synthesis techniques, employing direct charge injection for Fractional spurious tone reduction and an integrated VCO (voltage-controlled oscillator) with an active inductor resonant tank. A 0.35 μm CMOS process is used for implementation.