Frequency-locked Loop Research Articles

An FLL Providing Real-Time Frequency Calibration for OOK Power Oscillator Transmitters

A frequency-locked loop (FLL) is proposed to provide a real-time frequency calibration for OOK power oscillator transmitters. This FLL incorporates a pulse-width detector (PWD) based on Time-Registers (TRs) to discriminate accurately between the carrier frequency and the preset target frequency during the data modulation. As a result, frequency calibration can be performed simultaneously with data modulation without interruption. A prototype of an OOK power oscillator transmitter integrated with the proposed FLL is implemented with onboard discrete electronic elements for demonstration. The measurement indicates that the FLL can accurately lock to a carrier frequency of 160MHz despite electromagnetic (EM) interference in the loop antenna of the transmitter. In contrast, with EM interference and charge leakage, the carrier frequency differs from the expected value by about 1 MHz when the FLL is disabled.

A 0.9-V 6400-μm2 Resistor-Based Temperature Sensor With a One-Point Trimmed 3σ Inaccuracy of ±0.64 °C from −50°C to 125 °C

This paper describes a compact and precise resistive temperature sensor based on a frequency-locked loop (FLL) intended for thermal monitoring in system-on-chips. The FLL incorporates a switched-capacitor loop filter improving the sensors inaccuracy and FLL outputs are converted into a digital code with an edge-combined counter for efficient frequency-to-digital conversion. A prototype sensor is fabricated in 65-nm CMOS process and occupies only 6,400 μm2. It achieves a one-point trimmed 3σ inaccuracy of 10.64 ∘C over a wide temperature range of.50 to 125 ∘C. Operating at 0.9 V supply, it consumes 40 μW and achieves 2.2 mK resolution in a 1-ms conversion time, which corresponds to a resolution FoM of 0.19 pJ7K2.

Frequency-Locked Loop Based New Automatic Phase-Shift Method for Active Islanding Detection of Three-Phase MicroGrid

This paper proposes an active Islanding Detection Method (IDM) integrating Frequency Locked-Loop (FLL) for the detection of voltage phase and frequency at the point of common coupling (PCC) and a modified Auto Phase Shift (APS) method for three-phase Distributed Energy Resource (DER) serving a local RLC load. The FLL is composed of a double second-order generalized integrator (DSOGI) to attenuate the harmonics and pass the fundamental positive sequence components in a frequency adaptive manner. Different from traditional APS methods, a new variable frequency term with an exponential factor is injected into the phase shift algorithm to reduce the region of Non-Detection Zone (NDZ). This modified approach enables the decentralized power generation system to detect the islanding phenomenon more quickly. Simulations and experimental tests conducted on a DG system on OPALRT (OP5600) and hardware test-bed demonstrate the behaviour of the proposed model within IEEE Standards. Additionally, a comparative evaluation was performed on the seamless transition of a microgrid (MG) from Grid-connected mode to Islanded mode and vice versa, using two different MGs, each having a single voltage source converter (VSC) and a local load but with control circuits incorporating DSOGI-FLL and ROGI-FLL respectively. Hardware testing results indicated that the control circuit based on ROGI-FLL demonstrated superior performance.

A Reconfigurable Tri-Mode Frequency-Locked Loop Readout Circuit for Biosensor Interfaces.

In this article, a frequency-locked loop (FLL) based multimodal readout integrated circuit (IC) for interfacing with off-chip temperature, electrochemical, and pH sensors is presented. By reconfiguring its switched-capacitor feedback network, the readout circuit is able to measure resistance, current, and voltage without additional active analog front-end circuits. A prototype IC was fabricated in a 0.18 μm CMOS process. Measured results show that when measuring resistance, the input-referred resistance resolution is 10.5 Ω for 100 Hz integration bandwidth. Using an off-chip thermistor, the readout circuit covers a temperature range of 0-75 °C and achieves an equivalent temperature resolution of 16.4 mKrms. In current mode, the readout circuit has an input range of 0.5μA and an input-referred current noise as low as 40.6 pArms for 100 Hz bandwidth. Interfacing with an on-chip potentiostat, glucose chronoamperometry is demonstrated. In voltage mode, a minimum input-referred voltage noise of 31.7 μVrms is achieved, and the IC can measure a pH range from 1.6 to 12 using a commercial pH probe. At a 1.2 V supply, power consumption of the readout circuit is below 10 μW for all three measurement modes. Additionally, the prototype IC includes an integrated wireless transmitter that implements on-off keying modulation, and a wireless multimodal sensing system utilizing the FLL-based readout circuit is demonstrated.

A 4 GHz FLL-less fast-locking sampling PLL with gain-boosted sampling phase-frequency detector in 28 nm CMOS

This paper presents a sampling PLL (SPLL) using a gain-boosted sampling phase-frequency detector (SPFD) to suppress in-band phase noise. The implementation of the SPFD eliminates the need for a frequency-locked loop (FLL). Additionally, a cycle slipping elimination (CSE) technique is incorporated into the SPFD to enhance the locking speed of the SPLL. The proposed SPFD achieves phase detection gain multiplication by sampling both rising and falling slopes simultaneously, effectively reducing the noise contribution of building blocks with low-pass characteristics without compromising the linear phase detection range. To enhance the reliability of the SPFD, a phase detection gain calibration strategy is proposed, involving a replica capacitor array and a successive approximation algorithm, ensuring a consistent phase detection gain. Moreover, by integrating capacitive coupled noise circulating (CCNC) technique and 2nd harmonic control (F2) technique, a low noise CCNC–F2 VCO is introduced to further suppress out-of-band phase noise of the SPLL. Implemented using a 28 nm CMOS process, the SPLL employing the SPFD and CCNC–F2 VCO achieves a fitted RMS jitter of 61 fs integrated from 10 kHz to 100 MHz at an operating frequency of 4 GHz. The SPLL consumes 20.1 mW, occupies an area of 0.26 mm2 and achieves a jitter figure-of-merit (FoM) of −251.3 dB.

Weakly Time-Variant SOGI-Based Frequency Derivative Estimator

Recent works revealed the inherent periodically-time-variant property of the second-order generalized integrator-based frequency-locked loop (SOGI-FLL). This work further finds that this property affects the frequency derivative estimation of SOGI-FLL under time-variant frequency. A weakly-time-variant frequency derivative estimator is thus given to overcome this problem. Besides, this estimator reduces the transient deviation of the frequency derivative during the voltage sag and phase jump. It is theoretically proved that this weakly-time-variant idea shrinks the variation range of the coupled time-variant coefficient between the frequency derivative and amplitude/phase error. Comparative tests are given to validate the claims.

A Novel Power Measurement Method Using Lock-In Amplifiers with a Frequency-Locked Loop

The extensive use of renewable energy systems with grid-connected inverters (GCIs) causes harmonic injection. Similarly, the imbalance in energy demand and supply causes frequency fluctuations. As a result of the increased harmonics and frequency fluctuations, the accuracy of power measurement using conventional methods continues to decline. Precision in power measurement is an essential factor for the billing and management of power supply and demand. Moreover, it is challenging to build a supply plan for the power demand and to manage the billing for the power consumption. To solve these problems, this paper proposes a novel method based on Lock-in Amplifier (LIA) and Lock-in Amplifier Frequency-Locked Loop (LIA-FLL) to measure the power with high precision and accuracy. The proposed method first tracks the variations in the input signal frequency using LIA-FLL and generates the updated reference signals for LIA. After that, the LIA is used to extract the accurate amplitude of each frequency component. The proposed method results in accurate and precise measurement, even with harmonics and frequency fluctuations. The validity of the proposed method is verified by comparing the power measurement results with the classical method, FFT, and ZERA COM3003 (a commercially available power measurement reference instrument).

A smart control for self-reliant single-phase, grid-tied photovoltaic-battery storage system

This paper presents a grid-tied, solar energy conversion-battery energy storage (BES) system with an autonomous control method for critical load applications. In order to improve grid current dynamics and ensure that balance power is exchanged as an active power with utility, direct current management of the voltage source converter utilizes least mean fourth method. The intermittent nature of solar photovoltaics also affects dynamics and power quality of grid current. A potential solution to such a situation evolves by using a bi-directional, DC/DC converter which interfaces an optimized-sized BES system with a DC link. Dual-loop DC/DC converter control keeps BES system charging and discharging current within pre-set limits and also simultaneously regulates DC link voltage. State-of-charge control gets incorporated through a dual-loop control to prevent BES from overcharging/deep-discharging. Dual-loop voltage control with harmonic compensation is used to manage load voltage amplitude and frequency in islanded mode. Auto-grid synchronization is realized by using a first-order, frequency-locked loop (FLL) technique. Using FLL also reduces dc offset, harmonics, and inter-harmonics even in distorted grid circumstances. The presented investigation also proposes a step-by-step controller parameter design procedure based on the frequency domain stability restrictions. Experimental results using OPAL RT-5600 validate the expected system response.

Encoderless Control of PMa-SynRG Based-Stator Current Vector for Wind Generation Systems

In this paper, a novel encoderless control of permanent magnet assisted synchronous reluctance generator (PMa-SynRG) based-stator current vector for renewable energy systems is presented. For the encoderless control, the PMa-SynRG rotor position angle along with rotor angular speed are estimated ultimately from the generator's stator currents, as the stator inductance is only requisite nevertheless the stator resistance. Indeed, this encoderless control technique employs one current control loop for regulating the magnitude of the stator current instead of employing two current control loops. For eliminating the current measurement noise and enhancing the phase angle tracking performance, a modified second-order generalized integrator frequency-locked loop (MSOGI-FLL) technique is employed and compared with the standard SOGI-FLL under different voltage/frequency conditions. The proposed technique has a simple computational implementation while accomplishing a rapid along with precise estimation performance of the PMa-SynRG rotor position angle and speed. The performance is validated using simulations and real-time hardware-in-the-loop Typhoon HIL implementation.

Active disturbance rejection control of three-phase LCL power conversion system under non-ideal grid conditions

Under non-ideal grid operating conditions such as unbalanced grid voltage and harmonic grid that are commonly found in microgrid conditions, the negative sequence components of the microgrid voltage interfere with the active and reactive current controls in the power conversion system, leading to an increase in the harmonic content of the grid-side current and affecting the power quality of the microgrid system. To solve these problems, firstly, the mathematical model of the LCL-type power conversion system is analyzed, and a linear active disturbance rejection control based on model compensation is designed. Secondly, the influence of non-ideal power grid conditions on the control of the LCL-type power conversion system is analyzed, and the active disturbance rejection control strategy of the LCL-type power conversion system based on frequency-locked loops with harmonic cancellation modules (HCM-FLL) is proposed, which speeds up the system, improves the system’s robustness, and reduces the harmonic content of the network measurement current under the condition of power grid voltage unbalance and harmonic power grid. Finally, by using the verification of MATLAB/Simulink simulation, the current power quality obviously under the condition of voltage unbalance and harmonic power grid is evidently improved by the proposed control strategy. When compared to the traditional control methods, the control strategy proposed in this study features a simple control structure, making it easy to implement in engineering without requiring high controller performance or additional circuits. This reduces design costs and provides a wide range of controller parameters, ensuring strong anti-interference performance without the need for frequent controller parameter adjustments.

Evaluation of Low-Complexity Adaptive Full Direct-State Kalman Filter for Robust GNSS Tracking.

This paper evaluates the implementation of a low-complexity adaptive full direct-state Kalman filter (DSKF) for robust tracking of global navigation satellite system (GNSS) signals. The full DSKF includes frequency locked loop (FLL), delay locked loop (DLL), and phase locked loop (PLL) tracking schemes. The DSKF implementation in real-time applications requires a high computational cost. Additionally, the DSKF performance decays in time-varying scenarios where the statistical distribution of the measurements changes due to noise, signal dynamics, multi-path, and non-line-of-sight effects. This study derives the full lookup table (LUT)-DSKF: a simplified full DSKF considering the steady-state convergence of the Kalman gain. Moreover, an extended version of the loop-bandwidth control algorithm (LBCA) is presented to adapt the response time of the full LUT-DSKF. This adaptive tracking technique aims to increase the synchronization robustness in time-varying scenarios. The proposed tracking architecture is implemented in an GNSS hardware receiver with an open software interface. Different configurations of the adaptive full LUT-DSKF are evaluated in simulated scenarios with different dynamics and noise cases for each implementation. The results confirm that the LBCA used in the FLL-assisted-PLL (FAP) is essential to maintain a position, velocity, and time (PVT) fix in high dynamics.

Stable-operation design and fabrication results of a battery-less wireless-sensor interface IC with a switched-capacitor frequency-locked-loop circuit

This paper describes a method of designing a wireless-sensor interface integrated circuit that operates without a battery. Stable operation at low power is realized by integrating three kinds of circuit techniques: (i) a radio-frequency backscatter circuit for wireless sensing without power consumption, (ii) a sensor interface circuit with a frequency-locked loop for stable operation, (iii) and an energy harvester circuit with a power management function for battery-less operation. The circuit was fabricated using 0.13 μm CMOS process technology for design verification. We realized battery-less wireless sensing with intermittent operation and achieved high stability against process, voltage and temperature variations. The sensor information was obtained from the frequency variation of the radio-frequency backscatter signal. The integrated circuit was operated with radio-frequency signal power input exceeding −5 dBm. The integrated circuit dissipated less than 107.5 μA. The communication distance was 0.8 m at 920 MHz for 250 mW equivalent isotopically radiated power.

A Ka-Band Low-EVM Subharmonically Injection-Locked FLL IQ Modulator Using Stacked-Boosting and Dual-Injection Technique

In this letter, a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Ka$ </tex-math></inline-formula> -band low error-vector-magnitude (EVM) subharmonically injection-locked frequency-locked loop (SILFLL) in-phase and quadrature (IQ) modulator is proposed using 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process. The proposed circuit consists of an SILFLL and four reflection-type modulators. A stacked-boosting technique is employed in the oscillation core to further extend the frequency up to 28 GHz, and a dual-injection technique is employed in the SILFLL to significantly widen the lock range. As the subharmonic number is 3, the measured phase noise at 1-MHz offset and jitter integrated from 1 kHz to 40 MHz are better than −120 dBc/Hz and 95 fs, respectively. Between 26.6 and 28.2 GHz, the proposed SILFLL IQ modulator features an EVM of within 8%, a phase error of 2°, and a magnitude error of 2% for various quadrature amplitude modulations (QAMs), and the modulation can be up to 64-QAM scheme. The work is suitable for a few advanced digital communications due to its high modulation quality.

A 20-μs Turn-On Time, 24-kHz Resolution, 1.5–100-MHz Digitally Programmable Temperature-Compensated Clock Generator

A clock generator using a fast-locking frequency-locked loop (FLL)-based RC oscillator and delta-sigma fractional dividers (FDIVs) to generate programmable temperature-insensitive output frequencies is presented. Successive approximation register (SAR) logic is used to speed up the locking of the FLL, and truncation error cancellation (TEC) is performed in FDIVs to reduce delta-sigma-induced jitter. A prototype clock generator fabricated in a 65-nm CMOS process generates output clocks in the range of 1.5–100 MHz with a resolution of 24-kHz, 140-ps peak-to-peak period jitter, 6.8-ppm/°C inaccuracy, and can be turned on within 20 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> .

Synchronization and Control of a Single-Phase Grid-Tied Inverter under Harmonic Distortion

Grid-connected inverters in renewable energy systems must provide high-quality power to the grid according to regulatory standards such as the IEEE 1547. To provide high-quality current control when the inverter is connected to a distorted grid, the frequency and phase information of the fundamental harmonic of the grid should be accurately obtained. This paper examines controller design for a single-phase inverter when there is distortion in the grid voltage. The control structure is designed to enhance the quality of the injected current into the grid. To this end, a frequency-locked loop (FLL) sinusoidal tracking controller which is able to reject the grid harmonics is proposed. Thus, the contribution of this paper is a new frequency-locked loop structure with adaptive notch filters that can provide accurate estimation of grid phase and frequency and improve the performance of single-phase inverters working under harmonic distortion. We also present an explanation of how the proposed adaptive nonlinear scheme can be discretized for digital implementation on a microcontroller. Experimental and simulation results are presented to demonstrate the performance of the proposed controller in eliminating distortion and enhancing the quality of the produced power.

A Novel Dead-Time Elimination Method for Voltage Source Multilevel Converters

Voltage source multilevel converters (MLCs) are widely applied in recent years in a wide range of industrial applications. However, time delay inserted in switching signals to prevent short through can cause the dead-time effects, including output waveform distortion and voltage drop. In many kinds of MLCs, the freewheeling paths during dead time can also produce unexpected output voltage levels, which can cross a few consecutive output levels, introducing large <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv</i> / <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dt</i> . Typical examples of those MLCs are 5L-active neutral-point-clamped, 7L-hybrid-clamped, 4L-nested neutral-point-clamped (NNPC) converter, etc. To solve this problem, a generic dead-time elimination (DTE) method is proposed. This method splits the complementary switches and replaces them with controllable switches coupled with uncontrollable diodes, decomposing the phase-leg of the converter into two basic switching cells, thus obviating the need for dead time. To address the zero-current clamping effect inherent to the DTE method, a second-order generalized integrator frequency-locked loop based current detector is also developed. The proposed DTE method is suitable for various MLCs. It cannot only effectively eliminate the unexpected levels, but also significantly reduce the output distortion and regains the output rms value. An application example of 4L-NNPC converter is given. The effectiveness of the proposed method is verified by both simulation and experiment.

Design and Analysis of a Resistive Frequency-Locked Oscillator With Long-Term Stability Using Double Chopper Stabilization

A resistive frequency-locked loop on-chip oscillator based on a double chopper stabilization technique is proposed for the improvement of frequency stability. The temperature-sensitive nonidealities, including the reference mismatch current and amplifier offset voltage, are suppressed by a double chopper stabilization technique. A prototype chip is implemented in a 180-nm CMOS process with an active area of 0.3 mm2. The measurement results show that the frequency-locked oscillator operating at 250 kHz achieves temperature stability of 27.1 ppm/°C and long-term stability of 2.73 ppm, with the power consumption of 293 nW. The mitigation of the low-frequency flicker noise results in a 16X improvement in the long-term stability of the RFLO compared to that with no chopper technique.

Multi-Parameter Adaptive Notch Filter (MPANF) for Enhanced Interference Mitigation

<h3>Abstract</h3> Interference signals degrade global navigation satellite system (GNSS) performance and must be mitigated. Chirp signals can be mitigated with an adaptive notch filter (ANF), but the dynamic behavior limits performance. An ANF determines the instantaneous frequency and removes interference with a notch filter. However, there are several limitations. In this article, we propose a multi-parameter adaptive notch filter (MPANF) approach that significantly enhances conventional ANFs. First, it uses an loop-bandwidth control algorithm (LBCA) to alter the loop bandwidth of an frequency-locked loop (FLL)-based adaptation algorithm to facilitate superior tracking agility-to-precision trade-off. Second, it dynamically adjusts the notch depth to switch on interference mitigation or pass the signal through. Third, it modifies the notch width to accommodate tracking stability and optimize interference signal suppression to GNSS signal removal. The presented MPANF exhibits superior performance against chirp signals, including faster response to jump discontinuities.

GPS Receiver VFLL-Assisted PLL High Dynamic Weak Signal Tracking Based on a Maximum Likelihood Estimation

This paper proposes a GPS receiver vector frequency-locked loop-assisted phase-locked loop (VFAPLL) structure based on the maximum likelihood estimation (MLE) method for highly dynamic weak-signal scenarios. In this structure, the loop structure does not include a frequency discriminator, and the signal is directly input to the navigation filter after down-conversion, coherent integration, and other processing to avoid nonlinear noise error. Due to the high dimension and nonlinearity of the cost function of the MLE algorithm, the Levenberg Marquardt (LM) algorithm is used to optimize it. The proposed VFAPLL is compared with the VFAPLL implemented based on the extended Kalman filter (EKF) algorithm and the frequency locked loop assisted phase locked loop (FAPLL) implemented based on MLE. Through simulation verification, it was shown that the VFAPLL (MLE) has higher tracking accuracy, lower loss-of-lock threshold, and better robustness to the input signal than the other two loops.

Integrated control algorithm for fast and accurate detection of the voltage sag with low voltage ride-through (LVRT) enhancement for doubly-fed induction generator (DFIG) based wind turbines

Low voltage ride-through (LVRT) is one of the essential aspects of grid codes for integrating doubly-fed induction generators (DFIG) to achieve reliable and uninterrupted electrical power generation. The detection time of the voltage sag is one of the crucial aspects for the LVRT improvement of the DFIG. This paper introduces a second-order generalized integrator (SOGI), quadrature signal generator (QSG) with a frequency locked loop (FLL) based algorithm to detect the symmetrical voltage sag fast and accurately. The proposed SOGI-QSG-FLL-based voltage sag detection algorithm (VSDA) works under a second-order band-pass filter with an alfa-beta stationary reference frame. The proposed VSDA is integrated with the novel feed-forward transient current compensation (FFTCC) scheme with an advanced interval type-2 fuzzy logic-proportional integral (IT2-FLC-PI) controller to enhance the LVRT capability of the DFIG. This FFTCC scheme is activated after the detection of voltage sag by using the proposed VSDA. The proposed FFTCC feeds the uninterrupted active and reactive power to the grid and reduces the torque ripple of the DFIG. The detection time of voltage sag by using the proposed VSDA is compared with existing algorithms. The experimental results are also presented to validate the proposed algorithm.