Frequency-locked Loop Research Articles

A 32-MHz, 34-μW Temperature-Compensated RC Oscillator Using Pulse Density Modulated Resistors

Highly stable on-chip frequency references offer the possibility of replacing crystal oscillators in many cost-and form-factor-constrained applications. However, achieving good frequency stability in a power-efficient manner across process, voltage, and temperature variations possess many design challenges. This article describes these challenges and presents a method for improving the integrated RC oscillator’s frequency accuracy by overcoming them. We show that the impact of resistor temperature coefficient (TC) on the accuracy of output frequency can be mitigated by using a parallel combination of two switched resistors that are digitally controlled by pulse-density modulated sequences. By trimming at only two temperatures, a prototype frequency-locked loop (FLL)-based 32-MHz oscillator fabricated in a 65-nm CMOS process achieves an inaccuracy of 530 ppm (8.4 ppm/°C), 80-ppm/V voltage sensitivity, 2.5-ppm Allan deviation, and 1- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> /MHz power efficiency.

Enhanced Control of Three-Phase Grid-Connected Renewables with Fault Ride-Through Capability under Voltage Sags

The uninterruptible operation of grid-connected renewables under the occurrence of grid voltage sags is addressed in this work. This is achieved due to the incorporation of an enhanced control algorithm of a renewable source. The low-voltage ride-through algorithm was developed in accordance to the voltage profile introduced by IEC 61400-21 regarding grid voltage sags. To guarantee continuous operation of the renewable agent during voltage sags, not only instantaneous reactive power but also instantaneous active power under moderate voltage sags was injected to the utility grid fulfilling grid code requirements. A dual second-order generalized integrator frequency-locked loop synchronization algorithm was used to estimate the system’s frequency, together with the positive and the negative sequences of the three-phase utility grid voltages when unbalanced sags occurred. The current control was made in a stationary reference frame by using proportional-resonant regulators, and a DC voltage source was used to emulate the primary energy from any type of renewable system. The validation of the proposed control algorithm was conducted for a three-phase grid-connected renewable system with an apparent power of 500 kVA. The results from several experimental tests demonstrated the proper behavior of the enhanced algorithm.

JOINT TRACKING GPS AND LEO SIGNALS WITH ADAPTIVE VECTOR TRACKING LOOP IN CHALLENGING ENVIRONMENTS

Abstract. Navigation from LEO satellites own many merits and attracts increasing popularity recently. In addition to increasing the signal availability, the low signal strength loss and fast satellite geometry change from LEO satellite are particularly appealing in challenging environments. Recently, a few researchers attempt to navigate with non-cooperative signals from LEO satellites with pure phase lock loop (PLL) or frequency lock loop (FLL), while a more practical solution to utilizing LEO navigation is joint positioning with the existing GNSS signals which has not been seriously studied. In this study, we proposed a joint GPS and LEO navigation signal tracking strategy that employs a vector tracking loop (VTL) with fully considering the high dynamic characteristics of the LEO signals. In order to solve the high dynamics problem, the second-order deviation parameters were considered in the extended Kalman filter, which is more adaptive to the non-linear variation of the signal acceleration. In addition, a carrier-to-noise ratio (C/N0) based observation noise determination strategy is employed to adapt different observation conditions. The proposed method was verified with different simulation data and the results indicate the adaptive vector tracking loop is capable of tracking GPS and LEO signals simultaneously and robustly. The benefit is particularly in the weak signal scenarios. The experiment results also reveal that the joint vector tracking loop improves positioning accuracy in GNSS challenging environments.

An enhanced fast fundamental frequency estimator for three-phase electric aircraft grid

This article proposes a robust and enhanced three-phase fundamental frequency estimation algorithm for the electric aircraft grid. Unlike conventional frequency-locked loops, the digital signal processing technique-based frequency estimator proposed relies on the storage of five consecutive samples of the fundamental grid voltage signal. Furthermore, the ability to successfully operate at a low sampling frequency, i.e. 8 kHz, makes it sufficiently attractive as regards reducing the memory storage in a low-cost real-time controller. The proposed frequency estimator can additionally eliminate the negative effects of the DC-offset and the fundamental negative sequence components present in the grid signal without any additional effort. Also, the tuning efforts are reduced for the frequency variation range of 350–900 Hz owing to the existence of a single tuning gain parameter. The proposed algorithm has also been found to have a fast dynamic response, which has been experimentally validated through the use of a real-time digital controller.

Pseudo-Reference Counter-Based FLL for 6 Gb/s Reference-Less CDR in 65-nm CMOS

A 6 Gbps frequency-locked loop (FLL) for reference-less clock recovery loop has been designed. Based on the analyzed noise characteristic of the pseudo reference clock and the effect on the FLL output, we propose design strategies to decide the speed of the pseudo clock and the loop bandwidth for low phase noise. A non-linear digital sub loop enables the FLL to converge to the optimal noise bandwidth with a fast lock time. The proto-type reference-less clock recovery loop has been fabricated in 65 nm CMOS process and the FLL occupies 0.131 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip area. The FLL consumes 12.5 mW from 1 V supply and the measured output jitter is 4.13 ps,rms at 6 GHz.

Impedance Modeling of Three-Phase Grid-Connected Voltage Source Converters With Frequency-Locked-Loop-Based Synchronization Algorithms

With the increased installation of voltage source converters (VSCs) into the power grid, concerns about resonance/stability issues associated with interactions among converters, and between them and the ac grid is growing. The prevailing method for investigating these issues is the impedance modeling of VSCs, which involves linearizing all their control elements, such as their current control and grid synchronization system among others. In this process, most often a phase-locked loop (PLL) is considered for the grid synchronization of VSCs in the literature. The available options for the grid synchronization, however, are not limited to PLLs; a large number of frequency-locked loops (FLLs) for the grid synchronization of VSCs may also be found in the literature. The impedance modeling of three-phase VSCs equipped with FLL-based grid synchronization systems can be quite challenging as FLLs have different structures compared to PLLs. This article aims to address this difficulty. The general idea is obtaining the PLL counterparts of FLLs, which makes the VSC impedance modeling very straightforward. To make this idea clear, several case studies are presented and investigated.

A Poisson Process Generator Based on Multiple Thermal Noise Amplifiers for Parallel Stochastic Simulation of Biochemical Reactions

In this paper, we propose a novel Poisson process generator that uses multiple thermal noise amplifiers (TNAs) as a source of randomness and controls its event rate via a frequency-locked loop (FLL). The increase in the number of TNAs extends the effective bandwidth of amplified thermal noise and hence enhances the maximum event rate the proposed architecture can generate. Verilog-A simulation of the proposed Poisson process generator shows that its maximum event rate can be increased by a factor of 26.5 when the number of TNAs increases from 1 to 10. In order to realize parallel stochastic simulations of the biochemical reaction network, we present a fundamental reaction building block with continuous-time multiplication and addition using an AND gate and a 1-bit current-steering digital-to-analog converter, respectively. Stochastic biochemical reactions consisting of the fundamental reaction building blocks are simulated in Verilog-A, demonstrating that the simulation results are consistent with those of conventional Gillespie algorithm. An increase in the number of TNAs to accelerate the Poisson events and the use of digital AND gates for robust reaction rate calculations allow for faster and more accurate stochastic simulations of biochemical reactions than previous parallel stochastic simulators.

Adaptive odd repetitive control for magnetically suspended rotor harmonic currents suppression

Magnetic levitation rotating machinery has been widely used in industrial applications. Odd harmonic currents in the active magnetic bearing coils, which are caused by rotor mass unbalance and sensor runout, increase the power consumption and the base vibration. Repetitive control has recently been used to suppress harmonic currents in magnetic bearing systems. However, repetitive control needs the rotor rotational speed information and has some limitations without a speed sensor. In this paper, an adaptive odd repetitive control which does not need the speed sensors is proposed to suppress the active magnetic bearing odd harmonic currents. Compared to the conventional repetitive control, the second-order generalized integral frequency-locked loop is applied in adaptive odd repetitive control to estimate the rotor speed in real time without additional speed sensors. The magnetically suspended rotor with harmonic disturbances is modeled. The work principle, structure, and design of the adaptive odd repetitive control are addressed. The simulation and experiments are carried out on a rotor active magnetic bearing test rig to validate the effectiveness of the proposed adaptive odd repetitive control, and the results show that the active magnetic bearing odd harmonic currents are well suppressed.

A Second-Order Generalized Integrator Frequency Locked Loop With Damping Ratio Adaptation

The complex and ever-changing harmonics in grid voltage will cause performance deterioration of the frequency-locked loops (FLLs). Although various measurements had been adopted to attenuate the deterioration, they had to make the tradeoff between the dynamic and steady-state characteristics generally. Consequently, a novel single-phase FLL that can adaptively adjust the dynamic and steady-state performance was proposed in this article. The proposed FLL regards the damping ratio of second-order generalized integrator-FLL (SOGI-FLL) as a time-varying parameter rather than a constant, and adjusts the damping ratio adaptively, so the proposed FLL was named SOGI-FLL with damping ratio adaptation (DASOGI-FLL). The adaptive mechanism is to decrease the damping ratio as frequency estimation error decreases and vice versa. To realize the mechanism, a novel variable was constructed to indirectly correlate the damping ratio with frequency estimation error. An objective function containing the constructed variable for damping ratio adaptation was designed, and the adaptive algorithm was derived by using the gradient ascent method. Then, the convergence analysis, parameter design, and digital implementation of the algorithm were elaborated. Finally, the results of simulation and experiment reveal that, benefits from the damping ratio adaptation, DASOGI-FLL can achieve rapid convergence, strong filtering capability, and high estimation accuracy simultaneously.

A Frequency-Locked Oscillator Using Complex RC Impedance IQ-Balancing

This article presents a frequency-locked loop (FLL) oscillator using an impedance-sensing frequency detector for use in fully-integrated, on-chip frequency references. By detecting the real and imaginary components of a complex RC impedance, the FLL can be locked into the pole frequency where both components are balanced. A phase-mixing technique is also introduced to reconfigure the output frequency without altering the amplifier operating voltage. A prototype chip demonstrating this IQ-balanced approach was designed and fabricated in a general-purpose 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process. From measured results across multiple dice, the prototype integrated circuit (IC) chips achieve a temperature stability of 22 ppm/°C from −40°C to 80 °C and 10-ppm Allan deviation at an average output frequency of 647 kHz with 1.27 pJ/cycle energy efficiency, and 34.4 ppm/°C from −40°C to 80 °C and 15-ppm Allan deviation at an average output frequency of 1.39 MHz with 0.89 pJ/cycle energy efficiency.

PLL- and FLL-Based Speed Estimation Schemes for Speed-Sensorless Control of Induction Motor Drives: Review and New Attempts

Phase-locked loops (PLLs) and frequency-locked loops (FLLs) are of importance in power and energy applications. Both technologies have been introduced to speed-sensorless- controlled motor drives, and increasing applications of PLLs and FLLs for speed estimation are foreseen. To enable a proper and good design, a thorough review of the PLL- and FLL-based speed estimation schemes is then provided in this article. It is revealed through the review that many PLL- and FLL-based estimation schemes fail to accurately track a frequency ramp (i.e., obvious estimation errors appear), which may lead to a compromised estimation accuracy when these schemes that are applied in induction motor drives operating during acceleration and deceleration processes. To address this, the proven speed estimation schemes together with new attempts are also presented in this article. Moreover, various challenges to the PLL- and FLL-based speed estimation schemes, including harmonics, dc offsets, and parameter variations, are considered when evaluating these schemes. Solutions to tackle these disturbances are accordingly presented. In addition, two representative estimation schemes are exemplified through experimental tests. Finally, further challenges in using the PLL- and FLL-based schemes for speed estimation are discussed.

An 8.55–17.11-GHz DDS FMCW Chirp Synthesizer PLL Based on Double-Edge Zero-Crossing Sampling PD With 51.7-fsrms Jitter and Fast Frequency Hopping

This article proposes a phase-locked loop (PLL) based on the direct digital synthesis (DDS)/digital-to-analog converter (DAC) and the double-edge zero-crossing sampling phase detector (DS-PD) for frequency-modulated continuous-wave (FMCW) radar. Its DS-PD and frequency divider are combined to achieve refined time resolution while effectively expanding the phase lock range, thus eliminating the frequency-locked loop (FLL). The DDS/DAC is used to generate FMCW signals while achieving fast frequency hopping. A differential eight switching current unit is proposed to implement an ultrahigh-speed time-interleaved DAC. The 8.55–17.11-GHz PLL prototype, fabricated in 65-nm CMOS, consumes 10.11 mW with 0.29-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area, while the DDS/DAC consumes 12.0 mW with a 0.16-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area. The measured in-band phase noise (PN) at a 17.11-GHz output is −120.2 dBc/Hz at a 1-MHz offset with a root-mean-square (rms) jitter of 51.7 fs. The reference spur is <−51 dBc. Finally, a figure-of-merit (FoM) value of −255.7 dB is obtained. The prototype PLL effectively generates fast (500 MHz/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.6~\mu \text{s}$ </tex-math></inline-formula> ) and precise (105-kHzrms frequency error) triangular chirps for FMCW radar applications.

Single-Phase Transfer Delay FLL With Enhanced Performance for Power System Applications

This article proposes a gradient descent-based transfer delay frequency-locked loop (FLL) (GDTD FLL) to effectively address the challenges of existing transfer delay-based FLLs in terms of unacceptable frequency and phase angle overshoots during variations in the supply voltage amplitude and distorted voltage conditions. In the proposed GDTD FLL, a linear model of the distorted single-phase supply voltage is developed and the error term is constructed. Consequently, the gradient descent algorithm is employed to drive the error term to zero and provide an estimate of the FLL expression from which frequency estimation is achieved. By designing the learning rate employed in the gradient descent algorithm, a degree of freedom is introduced in the proposed GDTD FLL, giving it the ability to achieve improved performance during variations in the supply voltage amplitude. Furthermore, a delay-based harmonic cancellation approach is developed to reject supply voltage harmonics in the FLL’s phase angle estimation. The effectiveness of the proposed GDTD FLL is verified in comparison with other single-phase FLL schemes through experimental studies where it is shown that the proposed GDTD FLL effectively addresses the challenges of existing delay-based FLLs in terms of peak frequency and phase angle overshoots, especially when the supply voltage undergoes amplitude variation or distortion.

An Iterative Filter for FLL-Assisted-PLL Carrier Tracking At Low $C/N_0$ and High Dynamic Conditions

This article presents an iterative frequency lock loop (FLL)-assisted-phase lock loop (PLL) (FPLL) design in state space according to the minimum mean square error criterion. This is achieved by constructing a high fidelity carrier signal model with the consideration of the non-Gaussian nonwhite measurement noise characteristics. Two popular arctangent discriminators, e.g., two-quadrant (Atan) and four-quadrant (Atan2) are used to produce the PLL and FLL measurements for FPLL, respectively. The filter gain is selected to minimize the trace of the error covariance matrix and an iteration approach to quickly compute the steady-state filter gain is introduced. The nonlinearity in the discriminator and filter behaviors in FPLL at low $C/N_0$ and high dynamic conditions are investigated. The closed-form expressions of the closed-loop transfer function as well as error transfer function are clarified. The thermal noise induced tracking jitters on each carrier state, e.g., phase, doppler, and doppler rate, are derived, analyzed, and verified via Monte Carlo simulation, accordingly. The theoretical properties show that the iterative FPLL achieves the following. 1) The comparable tracking performance to the well-designed PLL-only. 2) The enhanced tracking accuracy over the well-designed FLL-only. 3) The improved tracking sensitivity over the conventional Kalman filter-based FPLL (KF-FPLL), at low $C/N_0$ condition and high dynamic conditions.

Frequency-Locked Loop Based on Active Noise Cancellation Syncretized Two First-Order Low Pass Filters

To improve the performance of the frequency lock loop (FLL) under the conditions of a distorted power grid and unexpected noise, a new type of frequency locked loop (Al-FLL) is proposed, in which the AL-FLL prefilter is formed by fusing two first-order low-pass filters (LPFs) with an improved active noise cancellation (ANC) method. Firstly, the improved S function variable step size least mean square algorithm (I-SVSLMS) is discussed and its performance is verified under different signal to noise ratio conditions. Secondly, the function and parameter selection method of LPFs are described. Finally, the stability of the whole system is analyzed. In addition, the denoising work is completed in the synchronous reference frame and the output frequency of the FLL is fed back to the Park transform as the rotation frequency, which further improves the dynamic response and steady state performance of the FLL. The results of simulation and experiment verify the effectiveness and reliability of the proposed method. Compared with the FLL based on second-order generalized integrator (SOGI-FLL), the Comb Filter based on FLL (COMB-FLL), and the AL-FLL without frequency feedback (AL-NF-FLL), the AL-FLL has the advantages of small computation, fast response speed, and small steady-state errors, etc., and it is fully competent to work under the conditions of power grid distortion and unexpected noise.

A Digital Frequency Locked Loop With Minimum Computation Overhead for Heavily Distorted Single-Phase Grid Systems

Grid-connected converters require grid frequency and phase information for controlling the power injections into the grid. This information is achieved by a phase-locked loop (PLL) or frequency-locked loop (FLL) algorithms. The accuracy, reliability, and ease of implementation of the PLL/FLL algorithms in all grid conditions dictate the performance of the grid-connected converters. This article proposes a digital FLL for single-phase grid-connected systems. The proposed FLL tracks the frequency accurately, even in heavily distorted grid conditions. It uses a second-order generalized integrator (SOGI) as a pre-filter and a digital counter, based on the zero-crossing detection (ZCD) logic for estimating the grid frequency and phase angle. It does not require complex filters and tuning of multiple parameters. The implementation of the proposed FLL is simple and has less computational overhead. The ability of the proposed FLL to track the frequency and phase under various steady-state (dc-offset and harmonics) and transient (voltage sag, frequency drift, and phase jump) grid disturbances is tested in simulation using MATLAB/SIMULINK, and the results are reported. The experimental validation is done using a field programmable gate array (FPGA) controller in the laboratory. The proposed algorithm is able to track the estimates within 1.2 cycles of the grid voltage when tested under a heavy-distorted grid having 26.4% total harmonic distortion (THD). The measurement uncertainties and results of single-phase grid-connected inverter (GCI) using the proposed FLL are also presented.

A Fast Background Frequency Calibration Based on Intermittent Frequency Locked Loop for the Super-Regenerative Receive

The conventional phase-locked loops or frequency-locked loops should take time to calibrate the oscillator’s resonant frequency in a super-regenerative receiver (SRR) and severely disrupts the receiver’s operations. This paper proposes a novel intermittent frequency locked loop (IFLL) as a frequency synthesizer to continuously maintain the resonant frequency equal to the preset target frequency without interruption to the SRR. An analog loop mainly composed of a time-register-based frequency detector and a charge pump is proposed to achieve precise frequency detection during each SRR’s quenching period regardless of the inevitable initial phase error, and adjust SRR’s resonant frequency accordingly. An average fractional division scheme is adopted to improve IFLL’s frequency resolution to the level of the quenching frequency. The operations of the IFLL are analyzed with the z-domain transfer function, including the stability and frequency response. A prototype is built and tested. The measurement results show that the proposed IFLL only needs a calibration cycle of fewer than 50 μs to adjust SRR’s resonant frequency without interruption against its receiving. The real-time frequency error after calibration is smaller than 70 kHz. SRR opposes a sensitivity of -61.2 dBm @ 200 kbps and a 3-dB bandwidth of 2.2 MHz.

Modified Second Order Generalized Integrator-frequency Locked Loop Grid Synchronization for Single Phase Grid tied System Tuning and Experimentation Assessment

The phase-locked loop (PLL) is applied in grid-tied systems to synchronise converter operation with grid voltage, affecting converter stability and performance. Synchronous reference frame PLL (SRF-PLL) is a popular grid synchronisation method due to its simplicity and reliability. Normal SRF-PLL cannot suppress DC offset, causing basic frequency and phase oscillations.When a grid is irregular, its bandwidth should be reduced to ensure acceptable disturbance rejection without sacrificing detection speed. To enhance the phase-angle estimation speed and accuracy, the researchers modified structure by adding the pre/in-loop filter in advanced PLLs.The capacity to deliver improved dynamic response and reduced settling time without compromising system stability or the ability to eliminate disturbances is a major issue for PLLs. Among different control methods, SOGI-FLL (second-order generalised integrator-based frequency locked loop) had the best performance. It tracks grid voltage frequency precisely even when there is harmonics,voltage variations, frequency fluctuations, etc. In the event of a dc offset, the calculated frequency incorporates low frequency oscillations. A modified second-order generalised integrator frequency-locked loop (MSOGI-FLL) is presented in this work to address grid voltage anomalies of all types, including dc offset. Using the Waijung Block-set of MATLAB/Simulink, a Modified SOGI-FLL is realized and evaluated by applying abnormal grid voltage situations using a low-cost DSP-based STM32F407VGT microcontroller. The results demonstrate MSOGI-better FLL's performance in harsh circumstances.

An Enhanced Adaptive Frequency-Locked Loop Based on Fixed-Length Transfer Delay

The fixed-length transfer delay-based adaptive frequency-locked loop (TD-AFLL) has drawn much attention due to its concise structure and faster response speed than conventional second-order generalized integrator-based FLL. However, the application of TD-AFLL is still limited owing to the poor performance in terms of phase-angle/amplitude detection under distorted grid conditions. This paper explores an inherent input-output relationship of TD-AFLL, and a notch filter is employed to represent its filtering feature. Then a high-order filter is designed based on this notch filter, and an enhanced TD-AFLL (ETD-AFLL) with improved phase-angle/amplitude detection is further derived. The ETD-AFLL highly improves the phase-angle/amplitude detection accuracy under distorted grid conditions yet keeps the same fast response speed as TD-AFLL. In addition, the ETD-AFLL only requires a slightly additional computational cost. Experimental results are given to support the proposed ETD-AFLL.

Frequency Estimators for SOGI FLL: Modeling, Design, and Equivalence for FLL Advancements

Different frequency estimators have been reported for frequency-locked loop (FLL) implementations. One example is the widely employed gradient descent estimator in second-order generalized integrator (SOGI) FLL. Whether this estimator differs from those in some existing FLLs is unknown. Therefore, in this article, gradient descent and two other estimators with amplitude normalization in the stationary and synchronous reference frames are developed for SOGI FLL implementation. By obtaining linear model of SOGI FLL with the three estimators, equivalence of their FLL is established. Thus, it is shown that when the estimator parameters are designed based on the established equivalence, the FLL dynamics is dictated by the SOGI stage. Thus, research involving orthogonal signal generation is crucial to FLL’s rapid advancements. Furthermore, harmonic rejection in SOGI FLL with the estimators is considered where it is shown that SOGI FLL with amplitude normalization in the synchronous reference frame is ideal for applications involving harmonics.