Pseudo-Reference Counter-Based FLL for 6 Gb/s Reference-Less CDR in 65-nm CMOS

Abstract

A 6 Gbps frequency-locked loop (FLL) for reference-less clock recovery loop has been designed. Based on the analyzed noise characteristic of the pseudo reference clock and the effect on the FLL output, we propose design strategies to decide the speed of the pseudo clock and the loop bandwidth for low phase noise. A non-linear digital sub loop enables the FLL to converge to the optimal noise bandwidth with a fast lock time. The proto-type reference-less clock recovery loop has been fabricated in 65 nm CMOS process and the FLL occupies 0.131 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip area. The FLL consumes 12.5 mW from 1 V supply and the measured output jitter is 4.13 ps,rms at 6 GHz.