Low-Power Frequency-Locked Loop Circuit with Short Settling Time

Abstract

A phase-locked loop (PLL) is an important and commonly used electronic circuit in various electronic systems. Its main drawback is the use of an RC low-pass filter which takes up the majority of the PLL area on the chip. The RC low-pass filter is necessary to ensure the PLL stability. To mitigate this issue, a frequency-locked loop (FLL) is used because the stability of an FLL system depends on the Miller capacitance inside of the operational amplifier, which drastically reduces the capacitor size and thus the chip area. This paper presents the design of a fully integrated FLL based on a frequency-to-voltage converter (FVC). FVC is optimised so that it stabilises in just three clock cycles, which reduces the settling time of the entire FLL circuit. The voltage-controlled oscillator (VCO) is optimised for low power in all corners and for a wide input signal range. The circuit is implemented in a 180-nm CMOS process. Simulations show that the FLL circuit is functional in all voltage, temperature and technology corners. It has a short settling time while using a small amount of power and chip area compared to the conventional PLL designs.