Frequency-locked Loop Research Articles

Flux observer with adaptive parameter based on dual third-order generalized integrator frequency-locked loop

Flux observer with adaptive parameter based on dual third-order generalized integrator frequency-locked loop

GENERALIZATION OF THE TIME INFINITE IMPULSE RESPONSE DIGITAL FILTERS

This work describes the generalization of a new kind of infinite impulse response (IIR) digital filter to filter the pulse signal periods. This kind of digital filter was designed using the previously designed frequency-locked loops (FLL), which are based on the time measurement and processing of both the input and output periods. FLL is a linear discrete system. Starting from the general form of difference equation of the IIR FLL digital filter of the third and fourth orders, the transfer functions and Z transform of the outputs are developed for the IIR FLL digital filter of any order. To demonstrate the capabilities and utility of the general equations, they were applied to design a suitable IIR digital filter using a fourth-order FLL. The filtering abilities and the analyses in the frequency domain of the designed low pass IIR digital filter are demonstrated using the theory of IIR digital filter and the corresponding MATLAB tools. Analyses of the fourth-order IIR FLL digital filter were also performed in the time domain using computer simulation in MATLAB.

Online Mechanical Resonance Frequency Identification Method Based on an Improved Second-Order Generalized Integrator—Frequency-Locked Loop

To address the issue of mechanical resonance frequency detection in dual-inertia servo systems, this paper proposes an online identification method for mechanical resonance frequency using a low-pass filter and cascaded second-order generalized integrator—frequency-locked loop (LPF-CSOGI-FLL). Initially, the cascaded second-order generalized integrator—frequency-locked loop (CSOGI-FLL) is employed to eliminate the interference of direct current (DC) bias in resonance frequency identification. From a dual-stage structural perspective, the first second-order generalized integrator (SOGI-FLL) acts as a band-pass pre-filter to extract the mechanical resonance signal from the signal to be tested. The second SOGI-FLL generates a signal with equal amplitude and frequency to the mechanical resonance and obtains the frequency of the resonance signal through the frequency-locked loop. Subsequently, a low-pass filter (LPF) is applied to the frequency feedback loop of the second-stage SOGI-FLL, effectively reducing the oscillation of the estimated frequency. Finally, combining the CSOGI-FLL with an LPF forms a novel structure, namely, LPF-CSOGI-FLL. The results demonstrate that the proposed method significantly improves the detection accuracy of mechanical resonance frequency under various conditions. Compared to traditional offline techniques, this method overcomes the impact of resonance frequency drift and enhances system stability.

Comparison between FLL and PLL in frequency estimation to supply distributed virtual inertia

To connect renewable energy sources (e.g. solar or wind) on the grid, an inverter or electronic converter is used. However, a traditional inverter has no inertia in the face of frequency changes. Unlike the inertia of the rotor of a synchronous generator. Frequency variations are a product of the imbalance between the energy generated and the grid loads. If the frequency is too far from its nominal value or if the rate of change of frequency (RoCoF) is high, it can affect the synchronism of the generators that feed the grid. Therefore, power cuts are made in sectors on the grid, thus preventing instability from spreading to other sectors on the grid, which translates into large economic losses. Solutions such as inverters with virtual inertia (or emulated inertia) are a good alternative due to their structural simplicity and low cost, compared to other solutions such as synchronous condensers, for example. For the virtual inertial control strategy, the grid frequency needs to be measured. This article compares the use of a phase-locked loop (PLL) or a frequency-locked loop (FLL) for frequency estimation and its effect on inertia emulation. The proposed control designs are validated through simulations.

Control of DVR using enhanced transfer delay frequency-locked loop using sine–cosine optimization

Control of DVR using enhanced transfer delay frequency-locked loop using sine–cosine optimization

Neural Network Quadrature Signal Generator-Based Virtual Flux Estimation for Predictive Control of PWM Converters

In this paper, a frequency-adaptive neural network-based virtual flux (FANN-VF) estimator is developed for sensorless control of a pulse-width modulation converter under unbalanced and distorted grid conditions. This method exploits two parallel FANNs configured as quadrature signal generators. The VF fundamental positive and negative sequence components (PNSCs) are inherently separated in the estimator without employing any cascaded filters. A frequency-locked loop is introduced to accurately track the frequency variations. The estimated VF PNSCs are directly exploited to compute the power references in VF-based predictive direct power control scheme. The developed strategy ensures constant active power and sinusoidal current waveforms under nonideal grid conditions. Simulation and experimental tests are performed to verify the effectiveness of the proposed method.

A frequency meter based on Costas FLL for resonant accelerometers

The resonant accelerometer (RA) is an important part for high-performance inertial devices. And high accuracy frequency measurement is one of the key technology for RA. This paper developed a frequency meter based on Costas frequency lock loop (FLL). This structure is flexible as the analog input sinusodial voltage wave is converted into digital domain by an ADC and the frequency measurement function dealing with that voltage could be implemented only with digital circuits. The transfer function of the frequency meter is determined by the loop filter of the FLL and the closed system is always stable for PID controller. The noise in the loop is reshaped by a first order ∑-Δ modulator formed by the frequency meter loop, which relaxes the requirement for the accuracy of ADC. A test board for the frequency meter is implemented with a 24-bit ADC and FPGA, and achieves a noise of 1mHz/Hz at low frequency band, 7µHz/Hz around 50 Hz with a 40 kHz sinusodial input voltage.

Smooth Low-Speed Sensorless Control of Switched Reluctance Machine With Heavy Load

For the switched reluctance machine (SRM) with heavy load, the inductance of the conduction phase is nonlinear, which makes the sensorless control method based on the linear region of the phase inductance no longer applicable. Meanwhile, in the case of light or no load, the estimated rotor position will abruptly change at the connection points between neighboring segments, which has an impact on the estimation of the speed. In this paper, a low-speed sensorless control method for the SRM with heavy load is proposed. The idle-phase inductance is modeled over a wide rotor position range for position estimation, and a proportional gain decreasing type second-order generalized integrator based on a frequency-locked loop (SOGI-FLL) is constructed to estimate the speed while performing rotor position filtering. The effectiveness of the proposed method is experimentally verified with a 3-phase 12/8-pole SRM prototype, and the results show that the estimated rotor position and speed are accurate and smooth, which is beneficial to performance improvement of the sensorless control.

Performance Investigation of Hybrid Shipboard Microgrid using ESOGI-FLL Technique

The issue of reducing greenhouse gas (GHG) emissions from ships has garnered significant interest from stakeholders within the maritime industry. This work considers a hybrid shipboard microgrid powered by a battery energy storage (BES), solar photovoltaic array (SPVA), and diesel generator (DG) set. The enhanced second-order generalized integrator-based frequency-locked loop (ESOGI-FLL) technique synchronizes the DG set and the shore grid at different operating modes to supply uninterruptable power to loads. The propulsion motor, nonlinear service loads, DG set, and sources equipped with power-electronic inverter result in power quality challenges within a hybrid shipboard microgrid. Thus, the ESOGI-FLL algorithm is utilized for the mitigation of power quality issues of hybrid shipboard microgrid. The hybrid microgrid is modeled in MATLAB/Simulink at different operating conditions and validated on a real-time test simulator.

Delay-Tracking Loop for Frequency Estimation of Grid-Interfaced Inverter Under Distorted Conditions

Fast and accurate frequency estimation is difficult for grid-interfaced inverter under distorted grid conditions with off-nominal frequency. A popular solution considers the multiple second-order generalized integrator-based frequency-locked loop yet can hardly achieve a fast dynamic response under significant phase jump and voltage sag. Another solution uses an adaptive sliding window filter with an additional frequency estimator. However, it is challenging to handle numerical instability due to the adjusting marginally-stable resonator and the accumulation error. This letter proposes a delay-tracking loop to overcome these problems. This loop allows the delay length to track the frequency with an inherent harmonics rejection at off-nominal frequency. At the same time, the fast response speed is maintained, and the marginally stable resonator is avoided. Comparative experimental results validate the above claims.

Fast Inertial Response of PMSG-Based Wind Turbines with Optimized Frequency-Locked Loop

Fast Inertial Response of PMSG-Based Wind Turbines with Optimized Frequency-Locked Loop

The Study of SRM Sensorless Control Strategy Based on SOGI-FLL and ADRC-PLL Hybrid Algorithm

The inductance model used in traditional sensorless control methods for switched reluctance machines (SRMs) exhibits high-order harmonics. The precision of the motor may be impacted by the buildup of rotor estimate errors caused by these harmonics. To address this issue, this paper proposes a novel method for SRMs that employs a hybrid algorithm combining an enhanced second-order generalized integrator (SOGI)-based frequency-locked loop (FLL) and an active disturbance rejection control (ADRC)-based phase-locked loop (PLL). This approach involves coordinate transformation and parameter identification to reconstruct the motor inductance model. Rotor position errors are calculated using the unsaturated inductance difference method. In order to enhance the accuracy of motor position estimation, a hybrid algorithm is employed to efficiently filter out harmonic errors and mitigate the tremor effect caused by the rotor position differential algorithm. This hybrid algorithm enables the estimate of the motor’s speed and rotor position. A sensorless control simulation model was developed using a 12/8 pole SRM to assess the motor’s performance under varying load conditions. Based on the results obtained, it is established that the application of this method can accurately estimate the rotor’s position and rotational speed and thus improve the performance of position sensorless control. Ultimately, a prototype system for a switched reluctance motor was created, and the effectiveness and feasibility of the proposed control technique were confirmed through experimental validation. This presents an innovative approach to engineering practice.

An Ultra Low Power Integer-N PLL with a High-Gain Sampling Phase Detector for IOT Applications in 65 nm CMOS

A low-power and low-jitter 1.2 GHz Integer-N PLL (INPLL) is designed in a 65 nm standard CMOS process. A novel high-gain sampling phase detector (PD), which takes advantage of a transconductance (Gm) cell to boost the gain, is developed to increase the phase detection gain by ~100× compared to the Phase-Frequency Detectors (PFDs) used in conventional PLLs. Using this high detection gain, the noise contribution of the PFD and Charge Pump (CP), reference clock, and dividers on the PLL output is minimized, enabling low output jitter at low power, even when using low-frequency reference clocks. To provide a sufficient frequency locking range, an auxiliary frequency-locked loop (AFLL) is embedded within the INPLL. An integrated Lock Detector (LD) helps detect the INPLL locked state and disables the AFLL to save on power consumption and minimize its impact on the INPLL jitter. The proposed INPLL layout measures 700 µm × 350 µm, consumes 350 µW, and exhibits an integrated phase noise (IPN) of −37 dBc (from 10 kHz to 10 MHz), equivalent to 2.9 ps rms jitter, while keeping the spur level 64 dBc lower, resulting in jitter figure of Merit (FoMjitter) ~−236 dB.

A Microwave Sensor Based on Frequency-Locked Loop and Multiple Complementary Split-Ring Resonators for Retrieving Complex Permittivity of Liquid Samples

A Microwave Sensor Based on Frequency-Locked Loop and Multiple Complementary Split-Ring Resonators for Retrieving Complex Permittivity of Liquid Samples

A 2.4-GHz ring-VCO-based time-to-voltage conversion PLL achieving low-jitter and low-spur performance

Ring oscillator (RO)-based frequency synthesizers have been widely used in Systems on Chip (SoCs) due to their tiny active area and broad tuning range. However, they also experience significant spur and jitter. Based on an extensive evaluation of the factors of space, power usage, reference clock frequency, jitter, and reference spur. In order to achieve low jitter and low spurious, we present a time-to-voltage conversion phase-locked loop (TVC-PLL) based on a RO in this study. To achieve a wide range of adjustable phase-detection gain, we introduce a time-to-voltage converter (TVC-PD) as a phase detector. We suggest a pre-phase locked module based on orthogonal output clocks help with locking in order to address the problem of the limited phase detection range of conventional TVCs, which can only be used for frequency-locked loops (FLLs). According to simulation results, our suggested TVC-PLL is built using TSMC 65-nm CMOS, uses 4.053 mW of power, and occupies an active area of 0.024 mm2 at a working frequency of 2.4 GHz. It achieves an RMS jitter of 625.4 fs in the 10k to 100MHz frequency range, a reference spur of −77.7 dBc, and a figure-of-merit (FoMJ) of −238.0 dB.

Speed-Sensorless Control of Induction Motor Drives With a STA-FLL Speed Estimation Scheme

Speed-sensorless control (SSC) techniques enhance the overall reliability while reducing the cost, and thus become attractive in induction motors (IMs). Simplicity and flexibility are the main features that make phase-locked loop (PLL)- and frequency-locked loop (FLL)-based speed estimation schemes stand out among considerable estimation methods. However, many PLL and FLL schemes exhibit a poor estimation accuracy in the cases of acceleration and deceleration (AaD). Accordingly, an adaptive second-order generalized integrator-FLL (SOGI-FLL)-based scheme is introduced. While, the issue of the estimated speed feedback (ESF) in the adaptive SOGI-FLL scheme remains an obstacle. With the above, a speed estimation scheme that combines the super-twisting algorithm with an FLL (STA-FLL) is proposed for the SSC of IM drives in this paper. In the proposed STA-FLL scheme, an STA-based quadrature signal generator (STA-QSG) is properly designed, in which the ESF is cancelled to further ensure speed estimation. Moreover, a closed-loop flux observer is adopted in the implementation to enhance the proposed STA-FLL scheme in terms of disturbance mitigation. Experimental tests are performed to validate the proposed STA-FLL scheme.

A Frequency and Angle Feedforward Estimator for Unbalanced and Distorted Three-Phase Electric Grids

This work presents an open-loop frequency estimator able to deal with typical disturbances, yet exhibiting fast dynamics. The proposal is tested and compared experimentally against the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">orthogonal voltage decomposition</i> OVD approach, which is considered the state-of-the-art open-loop frequency estimator and the recently proposed AFPLL. The results verify that the proposed approach operates correctly under unbalancing, harmonics, noise, and interharmonics, and after frequency, phase, and amplitude jumps, while exhibiting settling times about <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mathbf {25\%}$</tex-math></inline-formula> better than the OVD, and a similar execution time. Furthermore, the proposed technique has a performance comparable to advanced <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">frequency-locked loops</i> , it is easy to tune, and thus, it could be seamlessly applied in typical synchronization tasks where PLLs are usually employed.

A 28-nm 368-fJ/Cycle, 0.43%/V Supply-Sensitivity, FLL-Based RC Oscillator Featuring Positive-TC-Only Resistors and ΔΣM-Based Trimming

This Brief presents a process-scaling-friendly frequency-locked-loop (FLL)-based RC oscillator. It features an R-R-C frequency-to-voltage converter that entails resistors with only the same-sign temperature coefficients. Together with a low-leakage switched-capacitor resistor and a delta-sigma-modulator-based trimming, our 71.8-MHz RC oscillator in 28-nm CMOS achieves a frequency inaccuracy of 77.6 ppm/0C, a 0.43%/V supply sensitivity, and an 11-psrms period jitter. The energy efficiency is 368 fJ/cycle.

Synchronous Vibration Force Suppression of Magnetically Suspended CMG Based on Modified Double SOGI-FLL

The mass imbalance of the rotor will produce the synchronous vibration force that is transmitted to the magnetically suspended control moment gyroscope (MSCMG) through the magnetic levitation stator, which affects the imaging performance of the satellite. The suppression of the synchronous vibration force needs the speed signal. In order to solve the synchronous vibration force of the MSCMG when the speed measurement sensor fails, this paper proposed an modified double second-order generalized integral frequency-locked loop (SOGI-FLL) method, which uses the frequency of the disturbance signal generated through the mass imbalance of the rotor to adaptively estimate the rotor speed and suppress the synchronous vibration force generated by the active magnetic bearing system. The phase compensation is introduced to ensure the stability of the system in full frequency band. The electromagnetic force is directly used as the input signal of the control algorithm to achieve zero magnetic force control. Simulation and experimental are carried out, and the results are given to prove that the algorithm proposed in this paper can accurately estimate the rotation speed and achieve the vibration force suppression in the full rotation speed range. It is of great significance for the high-precision control of the active magnetic bearing rotor system.

An FLL Providing Real-Time Frequency Calibration for OOK Power Oscillator Transmitters

A frequency-locked loop (FLL) is proposed to provide a real-time frequency calibration for OOK power oscillator transmitters. This FLL incorporates a pulse-width detector (PWD) based on Time-Registers (TRs) to discriminate accurately between the carrier frequency and the preset target frequency during the data modulation. As a result, frequency calibration can be performed simultaneously with data modulation without interruption. A prototype of an OOK power oscillator transmitter integrated with the proposed FLL is implemented with onboard discrete electronic elements for demonstration. The measurement indicates that the FLL can accurately lock to a carrier frequency of 160MHz despite electromagnetic (EM) interference in the loop antenna of the transmitter. In contrast, with EM interference and charge leakage, the carrier frequency differs from the expected value by about 1 MHz when the FLL is disabled.