Frequency Divider Research Articles

K-band CMOS voltage-controlled oscillator using tail current modulation with half-output frequency

A CMOS voltage-controlled oscillator (VCO) using half-oscillation frequency signals as switched biasing is proposed to simultaneously improve the phase noise and DC-to-RF conversion efficiency. The effect of the flicker noise caused by the tail current source, which is the dominant factor of the VCO phase noise, can be reduced by the modulation using the half-frequency signals of the output. The conversion efficiency of the proposed VCO is improved by the leakage of the second harmonics of the modulation signal at the drain node of the current source, which is the same as the oscillation frequency of the VCO, thereby increasing the output power. The differential half-frequency signals are generated in the frequency divider, designed with the current-mode logic for minimizing the effect of parasitic components at high-frequency operation, which constitutes the frequency synthesizer without any additional circuits. The proposed VCO with the divider was fabricated on the size of 0.4 × 0.61 mm2 using a 65-nm CMOS process, including all pads. The measurement results showed a tuning range of 11.2% at the K-band and a phase noise of –109.86 dBc/Hz at the 1-MHz offset. The peak output power and DC-to-RF efficiency were measured to be 0.95 dBm and 16.64%, respectively, at the supply voltage of 1.2 V. A figure of merit of the proposed VCO was calculated to be –188.03 dBc/Hz.

A compact and fully integrated FMCW radar transceiver combined with a dielectric lens

Abstract Electronic measurement systems in the THz frequency range are often bulky and expensive devices. While some compact single-chip systems operating in the high millimeter-wave frequency range have recently been published, compact measurement systems in the low THz frequency range are still rare. The emergence of new silicon-germanium (SiGe) semiconductor technologies allow the integration of system components, like oscillators, frequency multipliers, frequency dividers, and antennas, operating in the low THz frequency range, into a compact monolithic microwave integrated circuits (MMIC), which contains most components to implement a low-cost and compact frequency-modulated continuous-wave-radar transceiver. This article presents a single transceiver solution containing all necessary components. It introduces a $0.48\,\mathrm{THz}$ radar transceiver MMIC with a tuning range of $43\,\mathrm{GHz}$ and an output power of up to $-9.4\,\mathrm{dBm}$ in the SG13G3 $130\,\mathrm{nm}$ SiGe technology by IHP. The MMIC is complemented by a dielectric lens antenna design consisting of polytetrafluoroethylene, providing up to $39.3\,\mathrm d\mathrm B\mathrm i$ of directivity and half-power beam widths of 0.95∘ in transmit and receive direction. The suppression of clutter from unwanted targets deviating from antenna boresight more than 6∘ is higher than $24.6\,\mathrm d \mathrm B$ in E- and H-Plane.

Design of synchronous frequency dividers in 5‐nm FinFET CMOS technology

AbstractA method is presented for the design of high‐speed frequency dividers in which the divided output signals are phase aligned by means of a scheme based on cascaded retiming. The objective of the design method proposed is to break the accumulation of propagation delay occurring in a divider chain that may limit the speed of the phase synchronization. Compared to alternative approaches where the phase synchronization is achieved with additional logical gates applied to the divider outputs, the authors’ approach only uses latches that are identical to those already employed in the divider chain itself without any additional synchronization logic. Hence, a better uniformity and homogeneity of the layout can be achieved, which helps improve the phase balancing. The method proposed to design synchronous dividers has been implemented in 5‐nm FinFET CMOS technology by means of a synchronous 8b‐counter providing the division factors 1/2 through 1/256. Its output phase synchronization has been verified in measurements at 10 GHz. The measured power consumption is 720 μW and the silicon area of the divider implemented is 79 μm2.

Simulation design and analysis 9-level H-bridge single phase stepdown cyclo inverter

This DC-to-AC voltage converter is designed for output frequency controlled by a 9-level cascade H-bridge cyclo inverter with pulse width adjustment. The aim of the study was to determine the pattern and format of the voltage, output frequency, and Total Harmonic Distortion index of a 9-level IGBT cyclo inverter. The method used is to build a unidirectional power converter design modeling into 9 alternating levels with cyclo converter-controlled frequency settings using the Simulink MATLAB tool. The cyclo converter section is constructed with two P and N converters in a parallel arrangement. The frequency and trigger pulse width of both converters control the output voltage and frequency format of the cyclo inverter. The test results show a series of ladder waves with an output frequency, of (1/2f, 1/3f, 1/4f, 1/5f, 1/6f, 1/7f, 1/8f, 1/9f, and 1/10f). The simulation results show that the nth input frequency divider waveform is characterized by the emergence of a number of step pulses of n positive half cycles and negative half cycles. The Total Harmonic Distortion Index gets bigger when the system circuit is designed at a low frequency. This modeling can be implemented into a prototype that is used for variable-speed DC motor drivers.

Verilog-based digital clock design methodology

A digital electronic clock is a sophisticated instrument that employs digital circuits to render the timehours, minutes, and secondsin a digital format. This paper delves into the intricate design journey of creating a basic digital clock using the powerful Verilog HDL paired with a seven-segment digital tube. The core objective revolves around the realization of the clocks essential features, emphasizing both timing mechanics and its visual display. The architecture of the digital clock circuit is a seamless integration of three pivotal modules: the frequency divider, which ensures accurate time intervals; the counter, which keeps track of elapsed time; and the decoder, responsible for converting raw data into a format suitable for display. The clocks tangible representation of time is vividly brought to life on a light-emitting diode (LED) display of the seven-segment digital tube. This setup magnificently showcases two-digit representations for hours, minutes, and seconds, streamlining the users experience. Rigorous simulation revealed that the system adeptly meets its operational mandate, functioning seamlessly as a digital clock and thereby aligning perfectly with the stipulated design criteria.

UART communication protocol frame format explanation and application

Universal Asynchronous Transceiver (UART) is a Universal Serial Data Bus, hardware communication protocol using asynchronous serial communication in a configurable manner rate. In most embedded systems, microcontrollers and computers, UART plays an important communication role as a hardware communication protocol between devices to ensure the efficient transmission of communication data. The understanding and use of the UART protocol is crucial in our design process. In order to better understand. basic principle this protocol and realize the use of URAT, this paper introduces serial communication, UART frame format explanation, the working principle of UART, simulation of simple UART3. Depending on the source clock, also known as the Baud Clock, each heterogeneous device in a complete system may be able to create a distinct baud rate and connect with other devices over a UART interface. The fundamental tenet of the UART protocol stipulates that for proper communication, the transmitter and receiver must be set at the same baud rate. It also introduces several advanced designs and applications of UART with baud rate, namely UART with automatic frequency generator and frequency divider and Determination of UART Receiver Baud Rate Tolerance.

Design and Optimization of an Ultra-Low-Power Cross-Coupled LC VCO with a DFF Frequency Divider for 2.4 GHz RF Receivers Using 65 nm CMOS Technology

This article presents the design and optimization of a tunable quadrature differential LC CMOS voltage-controlled oscillator (VCO) with a D flip-flop (DFF) frequency divider. The VCO is designed for the low-power and low-phase-noise applications of 2.4 GHz IoT/BLE receivers and wireless sensor devices. The proposed design comprises the proper stacking of an LC VCO and a DFF frequency divider and is simulated using a TSMC 65 nm CMOS technology, and it has a tuning range of 4.4 to 5.7 GHz. The voltage headroom is preserved using a high-impedance on-chip passive inductor at the tail for filtering and enabling true differential operation. The VCO and frequency divider consume as low as 2.02 mW altogether, with the VCO section consuming only 0.47 mW. The active area of the chip including the pads is only 0.47 mm2. The designed VCO achieved a much better phase noise of −118.36 dBc/Hz at a 1 MHz offset frequency with 1.2 V supply voltages. The design produced a much better FoM of −196.44 dBc/Hz compared to other related research.

A Wideband and Low Reference Spur PLL with Clock Feedthrough Suppressed and Low Current Mismatch Charge Pump and Symmetrical CML Divider

This paper presents the design and performance analysis of a wideband charge-pump phase-locked loop (CPPLL) characterized by low reference spur and low phase noise. The proposed CPPLL, operating as a wideband phase-locked loop (PLL) with a reference frequency of 100 MHz, achieves a wide tuning range of 40% from 2.0 GHz to 3.0 GHz. A clock feedthrough suppressed charge pump with additional bias current branches is used to reduce the PLL’s loop reference spur. The 4-stage current mode logic (CML) divide-by-2/3 circuit is utilized in the frequency divider to achieve high-speed frequency division. The circuit of an AND gate and latch in the 2/3 divider adopts a full differential symmetric structure to minimize the phase error of high-frequency differential signals. The voltage-controlled oscillator (VCO) is designed to provide a wide tuning range while optimizing the trade-off between the phase noise and power consumption. The fabricated PLL is implemented using a 0.13 µm CMOS process. Experimental measurements reveal a reference spur of −74.39 dBc at an oscillation frequency of 2.4 GHz. Moreover, the CPPLL achieves phase noise of −102.55 dBc/Hz@100 kHz and −127.15 dBc/Hz@1 MHz, while consuming 33.6 mW under a 1.2 V supply voltage. The integrated root-mean-square (rms) jitter, measured from 10 kHz to 10 MHz, is 340.99 fs, and the figure-of-merit (FoM) is −234.08 dB at a carrier frequency of 2.4 GHz, highlighting the potential of the proposed PLL for integrated circuit applications.

Area and power efficient divide-by-32/33 dual-modulus pre-scaler using split-path TSPC with AVLS for frequency divider

Abstract Pre-scalers are electronic circuits used in phase-locked loops to multiply frequencies. This is achieved by dividing the high-frequency signals generated from a voltage-controlled oscillator. The high-frequency operation of pre-scaler circuits leads to significantly higher power consumption. To address this, D flip-flops (D-FF) realized using true-single phase clocking (TSPC) logic. The work suggests incorporating the Adaptive Voltage Level Source (AVLS) circuit with the Dual Modulus Pre-Scaler (DMPS) circuit to reduce power consumption. In addition to the incorporation of the AVLS circuit, pass transistor logic (PTL) used in the feedback, further minimizes transistors and power. This paper proposes three different designs for divide-by-32/33 DMPS circuit. The proposed-1 design combines regular TSPC-based D-FF with PTL in the feedback and an AVLS circuit, resulting in an average power reduction of 36.5%. The proposed-2 design employs split-path TSPC-based D-FF with logic gates and an AVLS circuit, achieving a power reduction of 46.9%. The proposed-3 design employs split-path TSPC-based D-FF with PTL in the feedback and an AVLS circuit, achieving a significant power reduction of 47.8% compared to the existing DMPS circuit and transistor count by 9.1%. The proposed circuits are realized using a CMOS 180 nm technology node. Cadence Virtuoso and Spectre tools are used. The proposed divide-by-32/33 DMPS circuits also realized in the CMOS 45 nm technology node to verify the functionality in the lower technology node. A power reduction of 46.86% observed when compared to the reference circuit. The proposed designs are both power- and area-efficient, making them promising solutions for minimizing power consumption in pre-scaler circuits.

Optical frequency divider: Capable of measuring optical frequency ratio in 22 digits

Recent advances in optical frequency standards and optical frequency combs (OFCs) have drawn wide attention since by transforming other quantities into frequency metrology, a higher measurement sensitivity or accuracy can be achieved. Among them, the search for dark matter, tests of relativity, and detection of gravitational wave anticipate even more precise frequency ratio measurement of optical signals, which challenges the state-of-the-art optical frequency standards and OFCs. Here, we report an optical frequency divider (OFD) based on a Ti:sapphire mode-locked laser, which can realize ultraprecise optical frequency ratio measurements and optical frequency division to other desired frequencies. The OFD is based on an OFC frequency-stabilized to a hydrogen maser, whose frequency noise in optical frequency division is subtracted via the transfer oscillator scheme. An optically referenced radio frequency time-base is introduced for the fine-tuning of the divisor and the reduction in division noise. Using the OFD, the frequency ratio between the fundamental and its second harmonic of a 1064 nm laser is measured with a fractional uncertainty of 3 × 10−22, nearly five times better than previous results. Meanwhile, we also report the ability to transport between laboratories, the long-term operation, and the multi-channel division of the OFD.

A 58-%-Lock-Range Divide-by-9 Injection-Locked Frequency Divider Using Harmonic-Control Technique

This paper presents a divide-by-9 injection-locked frequency divider (ILFD). It can lock onto about 6-GHz input with a locking range of 3.23 GHz (58%). The basic concept of the ILFD is based on employing self-gated multiple inputs into the multiple-stage ring oscillator. A wide lock range is also realized by adapting harmonic-control circuits, which can boost specific harmonics generated by mixing. The ILFD was fabricated using a 55-nm deeply depleted channel (DDC) CMOS process. It occupies an area of 0.0210mm2, and consumes a power of 14.4mW.

A 4–5.2 GHz PLL with 74.8 fs RMS jitter in 28 nm for RF Sampling Transceiver application

AbstractThis paper presents a novel ultra low jitter phase‐locked loop (PLL) circuit architecture for RF Sampling Transceiver. The programmable frequency divider with duty cycle expansion and the new phase frequency detector and charge pump circuit are used to solve the problem of voltage domain conversion of narrow pulses in the traditional high‐performance charge pump PLL structure. The traditional structure degrades charge pump linearity and noise, thus deteriorating overall jitter performance. Furthermore, voltage‐controlled oscillator uses the dual core structure and the second harmonic suppression technology, combined with the proposed new switching capacitor structure, and achieves −139.3 dBc/Hz phase noise at the 1 MHz frequency offset of the 5.2 GHz carrier under the open loop state. The PLL implemented in a standard Taiwan Semiconductor Manufacturing Company 28 nm process occupies a core area of 0.4 mm2 and generates a frequency ranging from 4 to 5.2 GHz using 50 MHz oscillator input, the power consumption is 40 mW. It achieves 74.8 fs root‐mean‐square jitter integrated from 10 KHz to 30 MHz. When the PLL output is divided by 2, the output phase noise at 1 MHz frequency offset is −125.75 dBc/Hz, and the PLL FoM is −246.

Implementation And Comparison of Different Stages of Current Starved CMOS Ring Oscillator – A Study

The ring oscillators serves as the fundamental building blocks in both digital and analog circuit design, as its extensive use is found in various electrical systems, including phase-locked loops, frequency dividers, and clock generators. This study gives a general overview of the ring oscillator circuit, including its workings, uses, and important design considerations. The ring oscillator generates timing signals for synchronous operation and is often employed as a clock generator in digital systems. It may also be used as a frequency divider to separate higher frequencies into lower ones. A closed loop is used to connect an odd number of inverting stages to create the ring oscillator circuit. An inverter, which is often built using complementary metal-oxide-semiconductor (CMOS) technology, is a component of every stage. By adding a delay to each step, the ring oscillator creates a self-sustaining oscillation. The development and comparison of 3, 5, and 7 stage ring oscillators for different performance metrics, as well as corner analysis for propagation delay and the effect of temperature on the operation of the ring oscillator was performed using Cadence Virtuoso with 90nm technology. This comparison of several phases of a current-starved (CS) ring oscillator offers an advantage to the best design with innovation based on the technology employed and outcomes from the corner analysis, which hasn't been done in any of the more recent researches.

A robust fusion bus frequency estimation method to improve frequency oscillation damping in power systems

AbstractThis paper proposes a new robust method for accurately and reliably estimating remote bus frequencies in a power system. Two different measurement sources for the remote bus frequency are considered, that is, the ideal Frequency Divider (FD) and the Synchronous Reference Frame Phase Locked Loops (SRF‐PLLs). Each measurement signal encounters different uncertainties and data quality issues. In this paper, both data sources are employed and fused together to better estimate the remote bus frequencies. To this end, the model structure of the power system is selected and an Unscented Kalman Filter (UKF) is utilized together with a fusion covariance intersection method to enhance the accuracy of the estimated bus frequency. Since the fusion estimation method fails in case of quality issues on both channels, a robust Generalized Maximum‐likelihood UKF (GM‐UKF) using a novel outlier detection criteria is developed. The impact of the resulting robust fusion filter on the estimation of the remote bus frequencies and on the performance of WAPSS, which makes use of the estimated frequencies as the feedback signal, is examined via simulations. The results demonstrate the excellent performance and reliability of the proposed method in dealing with noise filtering and outlier suppression while ensuring a high statistical efficiency.

A Study of Injection Locking in Oscillators and Frequency Dividers

A time-variant model provides a framework for understanding and modeling injection locking in oscillators and frequency dividers. Application of the model offers new insights and allows optimization for lock range and power consumption. Two prototypes with no tuning are realized in 28-nm CMOS technology. The first operates from 26 to 63 GHz while drawing 1.88 mW. The second achieves a range of 24–73 GHz with a power consumption of 4.76 mW.

A Q-Band CMOS Image-Rejection Receiver Integrated with LO and Frequency Dividers

This paper presents a Q-band image-rejection receiver using a 65 nm CMOS technology. For a high image-rejection ratio (IMRR), the Q-band receiver employs the Hartley architecture which consists of a Q-band low-noise amplifier, two down-conversion mixers, a 90° hybrid coupler, and two IF baluns. In addition, a Q-band fundamental voltage-controlled oscillator (VCO) and a frequency divider chain divided by 256 are integrated into the receiver for LO. A charge injection technique is employed in the mixers to reduce the DC power while maintaining a high conversion gain and linearity. The VCO adopts a cross-coupled topology to secure stable oscillation with high output power in the Q-band. The frequency divider chain is composed of an injection-locked frequency divider (ILFD) and a multi-stage current-mode logic (CML) divider to achieve a high division ratio of 256, which facilitates the LO signal locking to an external phase-locked loop. An inductive peaking is employed in the ILFD to widen the locking range. The Q-band image-rejection receiver exhibits a peak conversion gain of 16.4 dB at 43 GHz. The IMRR is no less than 35.6 dBc at the IF frequencies from 1.5 to 5 GHz.

Coexistence of Bloch and Parametric Mechanisms of High-Frequency Gain in Doped Superlattices

The detailed theoretical study of high-frequency signal gain, when a probe microwave signal is comparable to the AC pump electric field in a semiconductor superlattice, is presented. We identified conditions under which a doped superlattice biased by both DC and AC fields can generate or amplify high-frequency radiation composed of harmonics, half-harmonics, and fractional harmonics. Physical mechanisms behind the effects are discussed. It is revealed that in a general case, the amplification mechanism in superlattices is determined by the coexistence of both the phase-independent Bloch and phase-dependent parametric gain mechanisms. The interplay and contribution of these gain mechanisms can be adjusted by the sweeping AC pump strength and leveraging a proper phase between the pump and strong probe electric fields. Notably, a transition from the Bloch gain to the parametric gain, often naturally occurring as the amplitude of the amplified signal field grows, can facilitate an effective method of fractional harmonic generation in DC–AC-driven superlattices. The study also uncovers that the pure parametric generation of the fractional harmonics can be initiated via their ignition by switching the DC pump electric field. The findings open a promising avenue for the advancement of new miniature GHz–THz frequency generators, amplifiers, and dividers operating at room temperature.

A Design of a Dual Delay Line DLL with Wide Input Duty Cycle Range

This article describes a dual-controller dual-delay line delay lock loop (DC-DL DLL). The proposed DLL adopted a dual delay line structure, each delay line was composed of a coarse adjustment and a fine adjustment unit, and the dual delay lines had corresponding control units to reduce the mismatch between the delay lines, and it avoided the complicated design of duty cycle correction (DCC) circuit. A frequency divider was added to divide the input clock to achieve a wider input clock duty cycle adjustment. Additionally, a simple clock synthesis circuit was proposed to synthesize the required clock. The DLL design used the 25 nm process with a voltage of 1.2 V. The simulation results showed that at a working frequency of 1.6 GHz, the peak-to-peak jitter of the DC-DL DLL after locking was approximately 17.61 ps, the maximum output duty cycle error was about 1.3%, and the input duty cycle ranged from 20% to 80%, with a power consumption of 10.06 mW.

Design and Analysis of High Performance Frequency Divider in 32 nm CMOS Technology for Biomedical Applications

In this paper, a 3-bit frequency divider (FD) using a novel sense amplifier based flip-flop (SAFF) is presented and demonstrated. The delay in this design was meticulously improved resulting in better values of power delay product (PDP).The latching stage of the proposed design makes use of a novel single ended structure. Comparative analysis in 32 nm CMOS technology using T-SPICE revealed significant and quantitative differences between the proposed design and the existing designs. The PDP results were obtained for ±10% voltage variation, wide temperature range of -40 ℃ to 125 ℃ and at extreme corner cases. Results indicated that the PDP of the new design at nominal operating conditions decreased by minimum of 27.28% and maximum of 57.49%. The proposed design was also at par with available design in terms of area and power. The analysis on the FD proved the assertions that the proposed design is a feasible alternative for high performance applications.

Design of a multi-modulus divider with a wide frequency dividing range and low power consumption

A method of moduli expansion was presented to address the issue of wrongly altering the divider ratio at the boundary of the modulus expansion when multi-mode dividers (MMD) were utilized in fractional-N phase locked loops (PLLs). The multi-mode frequency divider was designed as the cascade of the 2/3 frequency dividers with an RS control terminal. Compared to traditional methods, only one OR gate is required for each modulus expansion, reducing the chip area. The 2/3 divider was designed using a True Single-Phase Clocked (TSPC) D-trigger structure, and each D-trigger uses a logic control technique with clearing and setting the number. An eight-stage multi-mode frequency divider with modulus expansion was developed using SMIC 55 nm CMOS technology. The simulation results demonstrated the large frequency divider range of the multi-mode frequency divider and its ability to carry out consistent switching operations over the 8–511 frequency divider range. The power consumption is 66.04W at a supply voltage of 1V, an input frequency of 2GHz, and an output frequency of 250MHz.