Frequency Compensation Technique Research Articles

A Fully Integrated K-Band Dual Down-Conversion Receiver for Radar Applications in 90 nm CMOS

A fully integrated K-band dual down-conversion receiver for phased array radar applications in 90 nm CMOS is presented. The receiver utilizes the dual down-conversion architecture to achieve superior performance. The integrated 1.15 GHz image-rejection filter (IRF) provides enough wideband (22 MHz) image rejection ratio at 140 MHz offset before the second down-conversion by utilizing the Q-enhancing and frequency staggering techniques to compensate the component loss. The low noise amplifier realizes the single-to-differential-ended conversion at the input with a transformer and achieves good common-mode rejection. The 70 MHz intermediate frequency baseband consists of two cascaded 3rd-order band-pass active RC filters (BPFs) and one automatic gain control (AGC) loop, with the integrator frequency compensation technique to lower down the requirements on the embedded Op-Amps. Two phase-locked loop (PLL) frequency synthesizers are integrated to provide the local oscillation (LO) signals for the down-conversions, where the matching of the charge-pump is improved by adding one extra current compensation branch. The measurements of the prototype show that the receiver converts the targeted mm-wave signal to 70 MHz intermediate frequency while achieving 8.3 dB noise figure (NF), 51-95 dB variable gain range and >45 dB image rejection ratio at 140 MHz offset with >22 MHz signal bandwidth. The receiver draws 74 mA current (excluding 2 PLLs) from the 1.2 V power supplies and occupies a core area of 4.58 × 0.53mm 2 (excluding 2 PLLs).

Multistage operational transconductance amplifier frequency compensation technique based on fully differential feedback stage

AbstractIn this article, a new configuration of a three‐stage Complementary metal‐oxide‐semiconductor (CMOS) operational transconductance amplifier (OTA) is proposed. It removes the feedforward path while simultaneously amplifying the feedback path in the compensation network. Also, the proposed circuit uses only one small compensation capacitor which makes it appropriate regarding die area. The approach behind is demonstrated through a successful design using 0.18‐μm CMOS technology. In fact, the simulated OTA shows better performance in comparison with other methods and achieved 20.2 MHz, 82°, and 124 dB as gain‐bandwidth product, phase margin, and DC gain, respectively, and consumes 545 μW @ 1.8 V.

Improved reversed nested miller frequency compensation technique based on current comparator for three-stage amplifiers

This paper attempts to propose a newly modified method to improve the frequency compensation of three-stage operational trans-conductance amplifiers. In the topology of the new frequency compensation, a current comparator is placed on the feedback path, while the common node of Miller compensation capacitors, the feedforward path, is removed by eliminating the right-half plane zero. This tremendously improves the phase margin, stability, and gain band width product. Compared with other available frequency compensation methods, the newly proposed method manages to improve the figure of merits and lower power consumption while significantly decreasing the dimensions of capacitors in the compensation network. The superiority of the new method over other conventional methods for reversed nested Miller compensation has been examined by a three stage amplifier that has been designed and simulated through a 180 nm standard library CMOS. The results indicate that the new amplifier has achieved a power consumption of 285 µW, gain band width product of 14 MHz, and phase margin of 86° with 100 pF capacitance load at the supply voltage of 1.8 V.

A 1.2-V 2.41-GHz Three-Stage CMOS OTA With Efficient Frequency Compensation Technique

A performance-boosting frequency-compensation technique, called feed-forward Gm-stage and regular Miller plus indirect compensation (FGRMIC), is presented in this paper. The proposed structure consists of three parts that ensure the stability and significantly improve the performance, such as gain–bandwidth product (GBW), slew rate, and sensitivity. The first part is a feed-forward transconductance stage, and the second part is a Miller capacitor in series with one resistor. The third part is an indirect compensation capacitor combined with a resistor. Detailed theoretical analysis and design considerations are provided to demonstrate the stability of the compensation scheme. Measurement results show that the implemented amplifier, driving a 2-pF load capacitance, achieves a GBW of 2.41 GHz with a phase margin of 82.6° while consuming 12.6 mW with a 1.2-V supply voltage in a TSMC 65-nm CMOS technology. Large-signal step response indicates that the implemented three-stage FGRMIC amplifier settles with 1% settling error within 1.41 ns.

A two-stage CMOS OTA with enhanced transconductance and DC-gain

An ultra-low-power process-insensitive two-stage OTA working in weak inversion region with enhanced transconductance and DC gain is presented in this paper. The proposed two-stage OTA is based on a bulk-driven input stage with rail-to-rail input voltage range, in which the bulk transconductance is enhanced by means of a partial positive-feedback loop. At the same time, a pseudo-cascode frequency compensation technique is applied in this design to improve the phase margin and accordingly, robust the stability of the proposed OTA. In addition, the proposed composite-transistor structure is used to improve output impedance of the two-stage OTA in weak inversion region. As a result, the improvement of DC gain and gain-bandwidth is obtained. Transistor-level simulations and results in UMC 0.18 $$\upmu \hbox {m}$$ CMOS process confirm the theoretical results. Simulated from a 0.5 V supply voltage, the proposed two-stage OTA achieves a 111.5 dB DC gain, a gain-bandwidth product of 9.5 kHz and a phase-margin of $$66^{\circ }$$ while driving a 15 pF load.

A Sub-Microwatt Class-AB Super Buffer: Frequency Compensation for Settling-Time Improvement

This brief presents a frequency compensation technique to improve the settling time in driving moderate capacitive load (10–20 pF) of a low-power ( $ {\mu }{\mathrm{ W}}$ ) class-AB super buffer, wherein previously reported super buffers exhibit poor stability performance. From post-layout simulations in a 0.18- $ {\mu }\text{m}$ CMOS process, the proposed super buffer—while driving a 10-pF load and consuming less than 1 ${\mu }\text{A}$ of quiescent current from a 1.2-V supply voltage—achieves a factor of 1.8 (positive output direction) and 5.1 (negative output direction) reduction in the settling time compared to before compensation. We also validated the proposed technique through the measurements of a super buffer built on a protoboard with commercial discrete MOS transistors.

High bandwidth transimpedance amplifier using FGMOS for low voltage operation

In this paper a novel CMOS design of transimpedance amplifier (TIA) suitable for low-voltage low-power application is presented. A floating gate metal oxide semiconductor (FGMOS) transistor is used here in common source configuration to provide active feedback along with a standard MOSFET which acts as input stage of the circuit. Main intend of this work is to minimize supply requirement with increased linearity. The circuit of TIA presented in this paper works only at 1V supply with small power consumption of 1.1mW. One of the popular frequency compensation techniques is shunt peaking technique. It is employed here to extend bandwidth. The transimpedance output and − 3dB bandwidth of proposed circuit are 37.7dBOhms and 13.5GHz, respectively. The input impedance and transfer function is evaluated using mathematical analysis and small signal model of circuit. This is observed that results are improved as compared to well known regulated common gate (RC-G) amplifier.

Frequency compensation of two stage CMOS circuit using negative capacitance and flipped voltage follower

This paper presents a new and compact two stage CMOS structure with enhanced gain-bandwidth product (GBW) and high slew rate. The frequency compensation technique employed here comprises of a negative capacitance cell and a flipped voltage follower (FVF). The use of negative capacitance lowers the parasitic capacitance of preceding stage and thereby achieves significant improvement in GBW. The FVF acts as a voltage buffer and exploits pole-zero cancellation technique. The required compensation capacitor is very small so it can save chip area. The workability of the proposed circuit has been verified by using Mentor Graphics Eldo simulation tool with TSMC CMOS 0.18 µm process parameters. The simulated results show a GBW of 1.2 GHz and average slew rate of 88 V/µs with a power consumption of 6.3 mW.

Improvement of Rubidium Clock’s Frequency-temperature Characteristic

The improvement of the widely used rubidium clock’s frequency-temperature characteristic is an important topic of research. Through the research of the working principle of the rubidium clock and the frequency-temperature characteristic of it, we put forward a kind of scheme based on frequency compensation technique, including realization circuit, signal processing method and optimal control method for frequency conversion process. By applying the scheme, a commercial rubidium clock frequencytemperature characteristic has been improved dramatically without a deterioration of the clock’s other performance parameters. Compared with the traditional one, the method proposed has some advantages such as easy realization, high stability, high precision, easy adjustment etc.

Design Procedure for Three-Stage CMOS OTAs with AC Boosting Frequency Compensation Technique

ABSTRACTAn analytic design guide to design a three-stage cascade CMOS operational amplifier compensated by AC boosting frequency compensation (ACBC) method is presented in this paper. The procedure allows electrical parameters such as gain bandwidth (GBW) product or phase margin to be related to the value of circuit elements such as aspect ratio or biasing currents of transistors. The presented design guide is suited for pencil-and-paper design and yields accurate performance without unnecessary circuit constraint introduction. Simulation results using TSMC 0.18 µm CMOS process verifies accuracy and robustness of proposed procedure. Various load capacitors and circuit conditions are simulated and, based on obtained results, the presented design guide is comprehensive and efficient since it leads us from frequency response parameters to aspect ratio of MOSFETs.

A Fast-Settling Three-Stage Amplifier Using Regular Miller Plus Reversed Indirect Compensation

A novel frequency compensation technique, named Regular Miller plus Reversed Indirect Compensation (RMRIC), is presented in this paper for fast-settling three-stage amplifiers. The RMRIC topology includes, on the one hand, a Miller capacitor combined with one nulling resistor connected between the first stage and the third stage, and on the other hand, an indirect compensation capacitor in series with a resistor added between the first and the second stage, which improves remarkably the performance such as gain---bandwidth product (GBW) and sensitivity of the proposed amplifier. Detailed design considerations are carried out to demonstrate the stability of the compensation technique. Circuit simulation results show the amplifier driving a 2-pF load capacitance achieves a 9.25-GHz GBW dissipating only 16.5 mW with a 1.2 V supply voltage using a TSMC 65 nm CMOS technology, which shows a significant improvement in figure of merits. The implemented amplifier reaches a settling time of 3.35 ns with 0.006 % accuracy.

A 55-GHz-Bandwidth Track-and-Hold Amplifier in 28-nm Low-Power CMOS

This brief presents a 25-GS/s track-and-hold amplifier (THA) implemented in a 28-nm low-power digital CMOS process. Given the intrinsic low-pass behavior of the THA core, a frequency compensation technique is employed to improve the bandwidth by increasing the input amplitude for higher frequencies. This enhances the small-signal bandwidth by almost 30% to 70 GHz. Large-signal measurements show a 3-dB corner frequency of 55 GHz, which enables a performance sufficient for time-interleaved analog-to-digital converter systems operating above 100 GS/s. At a peak-to-peak input amplitude of 400 mV, the total harmonic distortion is −32 dB for a 50-GHz input signal at a dc power consumption of 73 mW.

Indirect frequency compensation technique using flipped voltage follower cell

ABSTRACTIn this paper, a useful frequency compensation technique for a three-stage fully differential amplifier with a recycling folded cascode (RFC) input stage structure is presented. The proposed compensation technique is based on using flipped voltage follower (FVF) cell in the RFC structure. This approach merges improved cascode and indirect compensation techniques that the output node of the FVF cell is used for the second one. The proposed circuit yields a higher gain bandwidth (GBW) than the other indirect compensation techniques at the cost of a more complex design procedure. This idea is simulated using 0.18 µm CMOS technology. Simulation results show a 125 dB DC gain, a 41 V/µs slew rate, a 44 MHz GBW, and a phase margin of 76°. The amplifier consumes 695 µW while driving a 30-pF load.

High performance reversed nested Miller frequency compensation

This paper presents an enhanced technique to improve frequency compensation in three stages operational transconductance amplifiers (OTA). Based on the reversed nested Miller technique, it uses a current subtractor in the common node of the Miller capacitors, thus significantly improving the gain-band width product (GBW) while ensuring unconditional stability and removing the feed forward path. Also, compared to other existing frequency compensation techniques such as AC boosting compensation or active feedback frequency compensation, the proposed approach exhibits better figure of merits with less power consumption. The simulations of a three-stage OTA with 100 pF capacitive load exhibited 5 pF of total compensation capacitors, 63° phase margin and 4.75 MHz as GBW.

A two-stage rail-to-rail current mirror OTA for ultra-low-power applications

ABSTRACTIn this letter, an ultra-low-power, ultra-low-voltage operational transconductance amplifier (OTA) with full rail-to-rail input/output swing is presented. The proposed two-stage OTA is based on the bulk-driven current mirror (CM) amplifier topology with Gm-C frequency compensation technique. In addition, a transconductance boosting technique is used to enhance performance of the CM input stage structure. Simulation results in 0.18-μm metal-oxide semiconductor technology show the proposed OTA achieves a 85.8-dB DC gain and a gain bandwidth of 21.9 kHz while driving a 15-pF load. The amplifier consumes 292 nW @ 0.5 V, which makes it suitable for low-power applications.

A 0.0045- <inline-formula> <tex-math notation="TeX">$\hbox{mm}^{2}$</tex-math></inline-formula> 32.4- <inline-formula> <tex-math notation="TeX">$\mu\hbox{W} $</tex-math></inline-formula> Two-Stage Amplifier for pF-to-nF Load Using CM Frequency Compensation

This brief reports an embedded capacitor multiplier (CM) frequency compensation technique to realize an extremely compact micropower two-stage amplifier for wide capacitive load ( $C_{L} $ ) drivability. It features: 1) a valuable left half-plane zero to enhance the closed-loop stability over a wide range of $C_{L} $ ; 2) no extra bias circuit and power, as the CM is embedded into the first stage of the amplifier, and 3) only one very small (subpicofarad) compensation capacitor improving the transient settling and area efficiency. Detailed analytical treatments of the amplifier offer the critical insights for device sizing and optimization. Fabricated in 0.18- $\mu\hbox{m} $ CMOS, the amplifier measures 3.06-MHz unity-gain frequency (UGF), 1.76- $\hbox{V}/\mu\hbox{s}$ average slew rate (SR), and $74^{\circ}$ phase margin (PM) at 20-pF $C_{L}$ , and 0.22-MHz UGF, 0.049- $\hbox{V}/\mu\hbox{s}$ SR, and $59.8^{\circ}$ PM at 15-nF $C_{L}$ . The die size is 0.0045 $\hbox{mm}^{2}$ , and power is $32.4 \mu\hbox{W} $ at 1.2 V. Competitive large- and small-signal figures of merit are achieved with respect to the state of the art.

Low-voltage process-insensitive frequency compensation method for two-stage OTA with enhanced DC gain

A proposed low-voltage pseudo-cascode frequency compensation technique to improve the phase-margin of the two-stage OTA in weak-inversion region is introduced. Furthermore, a enhanced composite-transistor technique to increase the DC gain of the two-stage OTA in weak-inversion region is also presented in this paper. Both the proposed techniques achieve enhanced performance without requiring any additional power dissipation. To compare the performance advantages of the proposed techniques, two two-stage OTAs were designed in a UMC 0.18μm CMOS process. Simulation results show that the DC gain of the two-stage OTA with enhanced composite-transistor is increased by a factor of 17dB, the unity-gain bandwidth of the OTA with the proposed pseudo-cascode compensation technique improved 18%, the phase-margin of the OTA is increased by 33%, and it is maintained over a factor of 300 (from 5 to 1500nA) scaling in its bias current.

A new frequency compensation technique for three stages OTA by differential feedback path

AbstractA new single Miller capacitor for frequency compensation of three‐stage amplifier is proposed in this paper. In this scheme, a differential stage in which its negative and positive inputs are connected to the output and input nodes of third stage with a cascade capacitor forms the compensation block of a conventional three‐stage amplifier. Analysis shows that this configuration significantly improves the frequency domain performances of total circuit such as phase margin (PM) and gain‐bandwidth product (GBW) with just a very small amount of compensation capacitor. A three‐stage amplifier has been simulated with and without a differential feedback path in a 0.18 µm complementary metal–oxide–semiconductor (CMOS). The simulated amplifier with a 100 pF capacitive load achieved more than 9 MHz GBW and 83° PM while the compensation is less than 0.2% of load capacitor. An amplifier based on conventional nested Miller compensation can just achieve less than 0.23 MHz GBW with the same load, while using more than 100 pF as compensation capacitor. So this method shows an improvement of a factor of 40 in GBW and reduction of a factor of 550 in the size of compensation capacitor. It is a suitable strategy for ON‐CHIP compensation in comparison to other methods. Copyright © 2014 John Wiley & Sons, Ltd.

A FVF LDO Regulator With Dual-Summed Miller Frequency Compensation for Wide Load Capacitance Range Applications

This paper presents a proposed Flipped Voltage Follower (FVF) based output capacitorless low-dropout (OCL-LDO) regulator using Dual-Summed Miller Frequency Compensation (DSMFC) technique. Validated by UMC 65-nm CMOS process, the simulation results have shown that the proposed LDO regulator can be stabilized by a total compensation capacitance (CC) of 8 pF for a load capacitance (CL) ranging from 10 pF to 10 nF. It consumes 23.7 μA quiescent current with a 1.2 V supply voltage. With a dropout voltage of 200 mV, the LDO regulator can support a maximum 50 mA load current. It can settle in less than 1.7 μs with a 1% accuracy for the whole CL range. The proposed LDO regulator is comparable to other reported works in terms of figure-of-merit (FOM). Most significantly, it can drive the widest range of CL and achieve the highest CL(max)/CC ratio with respect to the counterparts.

Hybrid cascode feedforward compensation for nano-scale low-power ultra-area-efficient three-stage amplifiers

A modified frequency compensation technique is proposed for low-power area-efficient three-stage amplifiers driving medium to large capacitive loads. Coined hybrid cascode feedforward compensation (HCFC), the total compensation capacitor is divided and shared between two internal high-speed feedback loops instead of only one loop as is common in prior art. Detailed analysis of this technique shows significant improvement in terms of bandwidth and stability. This is verified for a 1.2-V amplifier driving a 500-pF capacitive load in 90-nm CMOS technology, where HCFC reduces the total capacitor size and improves the gain-bandwidth by at least 30% and 40% respectively, compared to the prevailing schemes.