Frequency Compensation Technique Research Articles

Comparison of the Frequency Compensation Techniques for CMOS Two-Stage Miller OTAs

Several design options are nowadays available for the frequency compensation of CMOS two-stage transconductance operational amplifiers, from the traditional Miller approach employing a nulling resistor or a voltage buffer, to a current buffer or the more modern current amplifier. However, designers have no results on the frequency performance achievable that allow to consciously choose the best approach to meet the prescribed specifications efficiently. In this paper, a comparison among the possible Miller approaches is carried out by exploiting an analytical figure of merit that expresses a tradeoff between gain-bandwidth product, load capacitance, and total transconductance for a given value of phase margin. Interesting and useful results, even unexpected, are found. The accuracy of the comparison is also validated through simulations.

Single Miller capacitor frequency compensation with nulling resistor for three‐stage amplifiers

AbstractA frequency compensation technique for three‐stage amplifiers is introduced. The proposed solution exploits only one Miller capacitor and a resistor in the compensation network. The straightness of the technique is used to design, using a standard CMOS 0.35‐µm process, a 1.5‐V OTA driving a 150‐pF load capacitor. The dc consumption is about 14µA at DC and a 1.8‐MHz gain–bandwidth product is obtained, providing significant improvement in both (MHzpF)/mA and ((V/µs)pF)/mA performance parameters. Copyright © 2007 John Wiley & Sons, Ltd.

A Frequency Offset Estimation Technique Based on CCK for a WLAN Receiver Design

This paper studies a frequency offset estimation and compensation technique taking advantage of complementary code keying (CCK) in a baseband architecture. The proposed technique can switch between coarse and fine frequency offset estimation subsystems in order to achieve lower estimation errors and lower bit-error rates (BERs). The architecture mainly exploits the specific characteristics of the CCK code set; thus it blindly extracts the frequency offset without any assistance from a training sequence. The proposed technique is very suitable to be employed in a CCK-based WLAN system for the purpose of increasing data transmission rate. Extensive computer simulations show that the proposed technique and its architecture realization exhibit superiority in overall system performance.

Improved Reversed Nested Miller Frequency Compensation Technique With Voltage Buffer and Resistor

This brief introduces and develops a novel frequency compensation technique for three-stage operational transconductance amplifiers. The new compensation topology exploits a voltage buffer and a nulling resistor to achieve a double pole-zero cancellation, occurring beyond the gain-bandwidth product. To verify the effectiveness of the compensation scheme, an amplifier has been fabricated in a standard 0.5-mum CMOS process. Experimental measurements are found to be in good agreement with the theoretical analysis and show an improvement in small-signal and large-signal performances

Analytical comparison of frequency compensation techniques in three‐stage amplifiers

AbstractIn this paper, design equations of the most common Nested Miller topologies are derived. Moreover, a coherent and comprehensive analytical comparison among the different topologies is also presented. In particular, after deriving design equations, following the approach previously proposed by the authors that have the phase margin as the main design parameter, the different solutions are compared by evaluating a novel figure of merit that expresses a trade‐off between gain‐bandwidth product, load capacitance and total transconductance, for equal values of phase margin. It is shown that there is no unique optimal solution as this depends on the load condition and the relative magnitude of the transconductance of each stage. From this point of view, the proposed comparison also provides useful design guidelines for the optimization of small‐signal performance. Simulations confirming the effectiveness of the comparison are also given. Copyright © 2006 John Wiley & Sons, Ltd.

A dual complex pole-zero cancellation frequency compensation with gain-enhanced stage for three-stage amplifier

A dual complex pole-zero cancellation (DCPC) frequency compensation technique with gain enhanced stage (GES) for three-stage amplifier is proposed in this paper. It uses one pair of complex zeros to cancel one pair of complex poles, resulting in feature that the frequency response of three-stage amplifier exhibits that of a single-pole system. Meanwhile, the effective transconductance of output stage can be greatly increased by several times which are equal to gain of GES, and the power dissipation can be decreased when a GES is introduced. Thus the gain-bandwidth (GBW) is expected to be increased about 10 times compared to the conventional nested miller compensation (NMC) approach. Moreover, this technique requires only one very small compensation capacitor even when driving a large load capacitor. A GBW of 1.23 MHz, DC gain of 111 dB, PM of 86° and power dissipation of 0.29 mW can be achieved for a load capacitor of 500 pF with a single Miller compensation capacitor of 14 pF at a ± 1 V supply in a standard 0.6-?m CMOS technology.

Transconductance with capacitances feedback compensation for multistage amplifiers

A new performance-boosting frequency compensation technique is presented, named Transconductance with Capacitances Feedback Compensation (TCFC). A transconductance stage and two capacitors introduce negative feedback to a three-stage amplifier, which significantly improves the performance such as gain-bandwidth product, slew rate, stability and sensitivity. An optimized TCFC amplifier has been implemented, and fabricated in a 0.35-/spl mu/m CMOS process. The TCFC amplifier driving a 150-pF load capacitor achieved 2.9-MHz gain-bandwidth product dissipating only 45-/spl mu/W power with a 1.5 V supply, which shows a significant improvement in MHz/spl middot/pF/mA performance.

Single Miller capacitor frequency compensation technique for low-power multistage amplifiers

Due to the rising demand for low-power portable battery-operated electronic devices, there is an increasing need for low-voltage low-power low-drop-out (LDO) regulators. This provides motivation for research on high-gain wide-bandwidth amplifiers driving large capacitive loads. These amplifiers serve as error amplifiers in low-voltage LDO regulators. Two low-power efficient three-stage amplifier topologies suitable for large capacitive load applications are introduced here: single Miller capacitor compensation (SMC) and single Miller capacitor feedforward compensation (SMFFC). Using a single Miller compensation capacitor in three-stage amplifiers can significantly reduce the total capacitor value, and therefore, the overall area of the amplifiers without influencing their stability. Pole-splitting and feedforward techniques are effectively combined to achieve better small-signal and large-signal performances. The 0.5-/spl mu/m CMOS amplifiers, SMC, and SMFFC driving a 25-k/spl Omega///120-pF load achieve 4.6-MHz and 9-MHz gain-bandwidth product, respectively, each dissipates less than 0.42 mW of power with a /spl plusmn/1-V power supply, and each occupies less than 0.02 mm/sup 2/ of silicon area.

A multi-loop voltage feedback filterless class-D switching audio amplifier using unipolar pulse-width-modulation

Voltage feedback is frequently used in class-D switching audio power amplifiers. This paper discusses the design and implementation of a low-cost filterless class-D, unipolar pulse-width modulation switching audio amplifier having a multi-loop voltage feedback scheme. Classical frequency-compensation techniques are used to design and stabilize the three voltage feedback loops implemented in this application. This design method proves to be a cost-effective solution for designing high-fidelity (hi-fi) audio amplifiers. The cost is reduced because no output filter is used, the required switching frequency is half of the one needed if bipolar PWM was used, and no current sensor is needed for feedback purposes. The output impedance is extremely low due to the reduction of the successive voltage loops, making the amplifier less load dependent. Simulation results show that a total harmonic distortion (THD) of 0.005% can be achieved using this topology, as well as a flat frequency response, free of phase distortion in the audio band. Experimental results show the feasibility of this control scheme, since a THD of 0.05% was achieved with a laboratory prototyped amplifier. A comparison of the performance of this audio amplifier with that of some commercial class-D audio amplifiers, reveals that our design can seriously compete with some of the ICs leading the market at a lower cost.

Gain-enhanced feedforward path compensation technique for pole-zero cancellation at heavy capacitive loads

An improved frequency compensation technique is presented in this paper. It is based on a cascade of a voltage amplifier and a transconductor to form a composite gain-enhanced feedforward stage in a two-stage amplifier so as to broaden the gain bandwidth via low-frequency pole-zero cancellation at heavy capacitive loads, but yet without increasing substantial power consumption. The technique has been confirmed by the experimental results. An operational amplifier has been designed to drive a capacitive load of 300 pF. The amplifier exhibits a dc gain of 87 dB, a gain bandwidth of 10.4 MHz at 63.7/spl deg/ phase margin, an average slew rate of 3.5 V//spl mu/s, a compensation capacitor of only 6 pF while consuming 2.45 mW at a 3-V supply in a standard 0.6-/spl mu/m CMOS technology.

Active-feedback frequency-compensation technique for low-power multistage amplifiers

An active-feedback frequency-compensation (AFFC) technique for low-power operational amplifiers is presented in this paper. With an active-feedback mechanism, a high-speed block separates the low-frequency high-gain path and high-frequency signal path such that high gain and wide bandwidth can be achieved simultaneously in the AFFC amplifier. The gain stage in the active-feedback network also reduces the size of the compensation capacitors such that the overall chip area of the amplifier becomes smaller and the slew rate is improved. Furthermore, the presence of a left-half-plane zero in the proposed AFFC topology improves the stability and settling behavior of the amplifier. Three-stage amplifiers based on AFFC and nested-Miller compensation (NMC) techniques have been implemented by a commercial 0.8-μm CMOS process. When driving a 120-pF capacitive load, the AFFC amplifier achieves over 100-dB dc gain, 4.5-MHz gain-bandwidth product (GBW) , 65° phase margin, and 1.5-V/μs average slew rate, while only dissipating 400-μW power at a 2-V supply. Compared to a three-stage NMC amplifier, the proposed AFFC amplifier provides improvement in both the GBW and slew rate by 11 times and reduces the chip area by 2.3 times without significant increase in the power consumption.

Analysis of multistage amplifier-frequency compensation

Frequency-compensation techniques of single-, two- and three-stage amplifiers based on Miller pole splitting and pole-zero cancellation are re-analyzed. The assumptions made, transfer functions, stability criteria, bandwidths, and important design issues of most of the reported topologies are included. Several proposed methods to improve the published topologies are given. In addition, simulations and experimental results are provided to verify the analysis and to prove the effectiveness of the proposed methods.

Three-stage large capacitive load amplifier with damping-factor-control frequency compensation

A novel damping-factor-control frequency compensation (DFCFC) technique is presented in this paper with detailed theoretical analysis, This compensation technique improves frequency response, transient response, and power supply rejection for amplifiers, especially when driving large capacitive loads, Moreover, the required compensation capacitors are small and can be easily integrated in commercial CMOS process. Amplifiers using DFCPC and nested Miller compensation (NMC) driving two capacitive loads, 100 and 1000 pF, were fabricated using a 0.8-/spl mu/m CMOS process with V/sub tn/=0.72 V and V/sub tp/=-0.75 V. For the DFCFC amplifier driving a 1000-pF load, a 1-MHz gain-bandwidth product, 51/spl deg/ phase margin, 0.33-V//spl mu/s slew rate, 3.54-/spl mu/s settling time, and 426-/spl mu/W power consumption are obtained with integrated compensation capacitors. Compared to the NMC amplifier, the frequency and transient responses of the DFCFC amplifier are improved by one order of magnitude with insignificant increase of the power consumption.

Computer-aided design of 3D microwave filter using quasi-planar highQu dielectric resonator

A dielectric resonator filter is proposed for high-speed data communication systems and for multilayer filter applications. The structure is composed of a partially metallized dielectric plate enclosed in a parallelepipedic cavity. This topology allows high integration in a planar-type environment. The proper excitation is ensured by coplanar lines directly integrated on the dielectric resonator. This structure, easily manufactured, is suitable for high frequency-filtering and power applications. In order to realize two- and four-pole filters without tuning, some new coupling and frequency compensation techniques are presented. To compensate for a parasitic effect, a direct optimization method is combined applying a global electromagnetic (EM) analysis to describe the four-pole filter. Some experiments are performed to verify the theoretical design. © 2000 John Wiley & Sons, Inc. Int J RF and Microwave CAE 10: 333–341, 2000.

Dynamic frequency compensation technique for switched-capacitor amplifiers

A dynamic frequency compensation technique is proposed for an opamp included in a switched-capacitor amplifier with offset voltage effect cancellation. This feature allows the small-signal and large-signal settling times to be significantly improved compared to those obtained when only classical static frequency compensation is used.

Feedforward compensation of the amplifier output stage for improved stability with capacitive loads

It is pointed out that the stability margin of an audio power amplifier is reduced by a pole in the loop-gain transfer function caused by shunt capacitance in the loudspeaker load. The problem is most severe in amplifiers with output stages that have a high output impedance before feedback. Because MOSFET devices can have an output impedance that is much higher than BJT (bipolar junction transistor) devices, amplifiers with MOSFET output stages are particularly susceptible to load-induced oscillations. A feedforward frequency compensation technique is described that bypasses the pole in the output stage caused by the load capacitance for improved stability of the amplifier.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A monolithic p-channel JFET quad op amp with in-package trim and enhanced gain-bandwidth product

An amplifier that uses an analog resistive trim element (trimistor) that can be reduced in value by Al/Si filaments formed by an alloying process is described. Filament generation and their lengths are controlled by current pulses through the element. A general in-package trim technique was developed using the trimistor and a high-voltage high-current diode, allowing the package pins to be multifunctional. This combination permits the input offset voltage for each channel of a quad op amp to be trimmed in the package to 10 /spl mu/V. The differential input stage utilizes JFET followers, which allows the separation of JFET/bipolar biasing currents. This results in a low offset voltage temperature coefficient (1/spl sigma/) of 2.5 /spl mu/V//spl deg/C. The gain-bandwidth product is enhanced over the unity-gain frequency by using a dual-doublet frequency-compensation technique. One doublet is defined using the JFET follower with feedforward capacitance, and the second doublet is formed by local positive AC feedback applied to the input current mirror. The amplifier is unity-gain stable, with a 100 MHz gain-bandwidth product (at 100 kHz) and 25 V//spl mu/S slew rate. The symmetrical quad layout is 80/spl times/120 mil/SUP 2/ with 6% of the area dedicated to trim. The die is suitable for a 14-pin narrow-body surface-mount package.

An improved frequency compensation technique for CMOS operational amplifiers

The commonly used two-stage CMOS operational amplifier suffers from two basic performance limitations due to the RC compensation network around the second gain stage. First, it provides stable operation for only a limited range of capacitive loads, and second, the power supply rejection shows severe degradation above the open-loop pole frequency. The technique described provides stable operation for a much larger range of capacitive loads, as well as much improved V/SUB BB/ power supply rejection over very wide bandwidths for the same basic operational amplifier circuit. The author presents a mathematical analysis of this new technique in terms of its frequency and noise characteristics followed by its implementation in all n-well CMOS process. Experimental results show 70-dB negative power supply rejection at 100 kHz and an input noise density of 58 nV/(Hz)/SUP 1/2/ at 1 kHz.

An integrated operational amplifier with novel HF behavior

There is a growing demand for integrated operational amplifiers that combine high gain with a large unity-gain bandwidth and a simple frequency compensation. A frequency-compensation technique is described that enables construction of multi-stage amplifiers without introducing compensation problems. The suggested solution is based on the elimination of stages in the high-frequency region, such that in this region only one stage determines the roll-off. A circuit diagram of an integrated operational amplifier with a gain of 15/spl times/10/SUP 3/, a unity-gain bandwidth of 25 MHz, and frequency compensation in accordance with the above principle of elimination is presented.