Low-voltage process-insensitive frequency compensation method for two-stage OTA with enhanced DC gain

Abstract

A proposed low-voltage pseudo-cascode frequency compensation technique to improve the phase-margin of the two-stage OTA in weak-inversion region is introduced. Furthermore, a enhanced composite-transistor technique to increase the DC gain of the two-stage OTA in weak-inversion region is also presented in this paper. Both the proposed techniques achieve enhanced performance without requiring any additional power dissipation. To compare the performance advantages of the proposed techniques, two two-stage OTAs were designed in a UMC 0.18μm CMOS process. Simulation results show that the DC gain of the two-stage OTA with enhanced composite-transistor is increased by a factor of 17dB, the unity-gain bandwidth of the OTA with the proposed pseudo-cascode compensation technique improved 18%, the phase-margin of the OTA is increased by 33%, and it is maintained over a factor of 300 (from 5 to 1500nA) scaling in its bias current.