fractional-N Frequency Synthesizer Research Articles

A 0.055 mm2 Total Area Triple-Loop Wideband Fractional-N All-Digital Phase-Locked Loop Architecture for 1.9–6.1 GHz Frequency Tuning

This paper presents a wideband fractional-N all-digital phase-locked loop (WBPLL) architecture featuring a triple-loop configuration capable of tuning frequencies from 1.9 to 6.1 GHz. The first and second loops, automatic frequency control (AFC) and counter-assisted phase-locked loop (CAPLL), respectively, perform coarse locking, while the third loop employs a digital sub-sampling architecture without a frequency divider for fine locking. In this third loop, fractional-N frequency synthesis is achieved using a delta-sigma modulator (DSM) and digital-to-time converter (DTC). To minimize area, digital modules such as counters, comparators, and differentiators used in the AFC and CAPLL loops are reused. Furthermore, a moving average filter (MAF) is employed to reduce the frequency overlap ratio of the digitally controlled oscillator (DCO) between the second and third loops, ensuring stable loop switching. The total power consumption of the WBPLL varies with the frequency range, consuming between 8.8 mW at the WBPLL minimum output frequency of 1.9 GHz and 12.8 mW at the WBPLL maximum output frequency of 6.1 GHz, all at a 1.0 V supply. Implemented in a 28 nm CMOS process, the WBPLL occupies an area of 0.055 mm2.

Investigation and Improvement on Self-Dithered MASH ΔΣ Modulator for Fractional-N Frequency Synthesis

Investigation and Improvement on Self-Dithered MASH ΔΣ Modulator for Fractional-N Frequency Synthesis

Insights into Architectural Spurs in High Performance Fractional-N Frequency Synthesizers

Insights into Architectural Spurs in High Performance Fractional-N Frequency Synthesizers

A fractional-N frequency synthesizer with phase synchronization and programmable phase control capability

A fractional-N frequency synthesizer (FS) with phase synchronization and programmable phase control capacity is proposed. The issue of phase inconsistency among multiple FSs caused by the shift of delta-sigma modulator (DSM) output sequence is solved by means of the dual DSM switching technique. Following the FS core, a resettable divider (R-DIV) is presented, which can not only expand the final output frequency range, but also eliminate the phase uncertainty incurred by uncontrollable initial states inherent in the ordinary dividers. By adding initial values to the first order accumulator in the third-order DSM, the output clock phase of the FS can be controlled accordingly. The simulation results show that from a supply voltage of 1.2 V, the frequency range of the FS is 0.4∼12 GHz, and the phase synchronization time is < 10 μs. The minimum phase shift step size of the programmable phase control is 5.625°, the RMS phase error is < 0.9°, and the power consumption is 113.7 mW.

0.18-μm CMOS process 40 MHz–4.41 GHz frequency synthesizer with high linearity low phase noise varactor-reconstruction LC-VCO

A 40 MHz–4.41 GHz fractional-N frequency synthesizer (FS) with varactor-reconstruction VCO (VRVCO) fabricated in the standard 0.18-μm CMOS process is demonstrated. In the conventional VCO, owing to non-linearity of varactor and parasitic effects of switched-MOSFET, the top and bottom of the tuning curves show nonlinearity. The novel design of VRVCO for tuning sensitivity base on series-shunt hybrid capacitor-varactor part and optimized switched-capacitor bank is incorporated into the 4.41 GHz FS design to reduce the variation of the VCO gain, realize high linearity tuning curves and improve phase noise performance. Furthermore, a noise reduction topology is adopted to decrease phase noise of VRVCO. Simulated results show the proposed VRVCO can improve linearity of tuning frequency over the entire tuning range. The measured results show the overall tuning range exceeds 115% from 1.92 to 4.41 GHz including three VRVCOs with high linearity (fine-tuning sensitivity: 131%, coarse-tuning sensitivity: 106%) and the phase noise is −120dBc/Hz at 1 MHz offset from the carrier frequency of 4.41 GHz.

CMOS Fractional-N Frequency Synthesizer for UHF RFID Reader Applications With Transformer-Based ISF Manipulation VCO

This brief presents the CMOS fractional-N frequency synthesizer for UHF RFID reader applications. With stringent phase noise (PN) specifications for UHF RFID transceiver, our proposed synthesizer is designed to have a narrow loop bandwidth and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2^{nd}$ </tex-math></inline-formula> -order loop filter as the optimum solution paired with low noise VCO. Then, we propose the transformer-based impulse sensitivity function (ISF) manipulating VCO that supports the target PN of the frequency synthesizer, albeit with large pass-band characteristic. Compared to conventional ISF manipulating VCO, our proposed solution improves the PN by 11.3 and 14.7 dB at 10 kHz and 1 MHz offset frequencies, respectively. Figure of merit (FOM) is also superior to conventional one by 7.4 and 10.9 dB at aforementioned offset frequencies. The frequency synthesizer is implemented in a 55nm CMOS technology as a part of the UHF RFID transmitter and consumes 38.4 mW power with 0.413 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$mm^{2}$ </tex-math></inline-formula> active area. With comparison to the state-of-the-art frequency synthesizer at sub-6GHz operating frequency, only our solution satisfies the target PN for EPC global standard and various local regulations across the entire UHF RFID operating frequency range.

Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise

This paper presents a novel technique to reduce the locking time in Digital Phase-Locked Loop (DPLL) based on Bang-Bang Phase Detector (BB-PD). The implemented 65-nm CMOS fractional-N frequency synthesizer generates an output signal between 3.7 and 4.1 GHz from a 52 MHz reference clock and improves the trade-off between phase noise, due to the loop quantization, and locking time, exploiting a digital locking loop that avoids look-up table (LUT) and finite state machine-based (FSM) locking schemes. Measurements show that the output signal spot noise at 20 MHz from the carrier is −150.7 dBc/Hz while the best locking time, for a coarse step of 364 MHz, is 115 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> , overcoming the locking time limitations and avoiding cycle slips that usually affect the 1-bit phase detector PLL.

A 3.2-GHz 405 fsrms Jitter –237.2 dB FoMJIT Ring-Based Fractional-N Synthesizer

A ring-oscillator (RO)-based low-jitter digital fractional-N frequency synthesizer is presented. It employs a frequency doubler (FD) that doubles the reference clock frequency, a 2-bit time-to-digital converter (TDC) with optimized thresholds to minimize the quantization error, and a high-resolution digital-to-time converter (DTC) to cancel the quantization error of the delta-sigma fractional divider (FDIV). DTC’s linearity is improved using a piecewise linear (PWL) function-based correction scheme. On-chip digital calibration is extensively used to correct imperfections of the FD, TDC, and DTC. A prototype synthesizer incorporating the proposed techniques and implemented in a 65-nm CMOS produces a 3.2-GHz output clock from a 96-MHz input clock. The worst-case integrated jitter is 306 and 405 fs in integer and fractional-N modes, respectively. The synthesizer consumes 11.7 mW from a 1-V supply of which 7.84 mW is consumed by the oscillator. The jitter figure-of-merit of the synthesizer is −237.2 dB.

A low power MASH digital delta-sigma modulator with accurate output average value

This paper presents a modified Multi-stAge noise Shaping (MASH) digital delta-sigma modulator (DDSM). The proposed structure has an accurate mean value and efficient randomization for all input values to reduce the spurious tones. In addition, the proposed MASH based Sigma Delta modulator has less hardware complexity and power consumption compared to conventional structures. The Verilog HDL-based simulations and experimental implementation on FPGA have been used to verify the randomization efficiency of the proposed structure. Power consumption and hardware complexity are verified by post-synthesis simulations. The randomization efficiency of the proposed MASH DDSM is also verified by phase noise simulation of the fractional-N frequency synthesizer.

A 0.023–12 GHz ultra-wideband frequency synthesizer with FOMT of −251.8 dB

A fully integrated ultra-wideband fractional-N frequency synthesizer is presented in this paper. Ultra-wideband quadrature signals can be generated by an octave-wide fractional-N phase-locked loop (PLL) and an ultra-wideband local oscillator (LO) signal generator. An optimized dual-core voltage-controlled oscillator (VCO) is employed to maintain relatively constant loop parameters in the octave-wide operating range, while a negative-capacitance VCO (NC–VCO) is proposed to solve the frequency gap problem and enhance the design freedom of the wideband VCO. Moreover, a wide-range programmable multi-modulus divider (PMMD) with seamless switching and fractional division resolution is proposed for error-free division operation and quantization noise compensation in the fractional-N mode, respectively. Power-efficient design is mainly achieved by the presented hybrid LO generator with optimized divider topologies for different frequency ranges. Fabricated in a 55 nm CMOS process, 0.023–12 GHz continuous quadrature LO signals can be generated by the proposed frequency synthesizer which occupies an active area of 0.55 mm2 and consumes 75–104 mW from a 1.2 V supply. The measured phase noise is −108.1 dBc/Hz at 1 MHz offset from a 12 GHz carrier, and the I/Q phase error is less than 2.7° with FOMT of −251.8 dB.

An integrated 0.0625–4 GHz quadrature-output fractional-N frequency synthesizer for software-defined radios

This paper presents a compact 0.0625–4 GHz fractional-N frequency synthesizer with quadrature phase output for software-defined radios (SDRs). Four voltage controlled oscillators (VCOs) and six cascaded dividers are used for wideband operation. Second harmonic filtering and high frequency noise suppression techniques are applied in VCO for phase noise optimization. Inverter switch and cascade switch buffers are combined for channel selection enhancement and output amplitude improvement. A large output voltage dynamic range with minimum current variation and mismatch is achieved by enabling transistors to work in triode region in charge pump. Implemented in a 55 nm CMOS process, the synthesizer demonstrates continuous frequency coverage from 62.5 to 4000 MHz with orthogonal output signals greater than 2 dBm while consuming 125 mW of power and provides the phase noise performance of −96.3/-127.7 dBc/Hz at 10 kHz/1 MHz offsets under a 2 GHz carrier. The chip area including all the pads and IOs is 3.34 mm2.

A 24-GHz Fully Integrated CMOS Transceiver for FMCW Radar Applications

A 24-GHz fully integrated frequency-modulated continuous wave (FMCW) direct conversion transceiver, implemented in a 55-nm low-power CMOS technology with a maximum <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{\mathrm {T}}$ </tex-math></inline-formula> of 190 GHz in typical operating conditions and packaged in a 5-mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 5-mm 32-lead quad-flat no-leads (QFN) package, is presented in this article. The single-chip transceiver uses a single 2.5-V supply while all the core circuits are powered by integrated regulators. The complex low-noise transductor in the receiver uses a quadrature hybrid to generate quadrature signals in the receiving front-end. The analog signal processing circuits including high-pass filters, low-pass filters, and programmable amplifiers are implemented following the receiver front-end circuitry. The FMCW signals are generated by an on-chip 24-GHz fractional-N frequency synthesizer. The synthesizer is completely integrated with the transceiver and provides built-in digital frequency modulation to generate chirping signals for the down-conversion local oscillator (LO) and the transmitted signals. The transmitter is composed of a balanced class-AB power amplifier driven by the FMCW signals from the frequency synthesizer.

Folded Noise Prediction in Nonlinear Fractional-N Frequency Synthesizers

The presence of nonlinearities in a fractional-N frequency synthesizer leads to the generation of an additional component of noise that appears in the output phase noise spectrum. This nonlinearity-induced noise component manifests itself as spurious tones and an elevated noise floor, also known as folded noise. This paper presents a mathematical analysis of the folded noise generated in fractional-N phase locked loops (PLL) by the interaction between the quantization noise introduced by the divider controller and a nonlinearity. The analysis is performed for different digital <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> modulators (DDSM) and nonlinearities, providing expressions that allow one to predict the folded noise. These are compared with state-of-the-art predictions and simulation results.

Spur Immunity in MASH-Based Fractional-N CP-PLLs With Polynomial Nonlinearities

Spurious tones appear in the output phase noise spectrum of a fractional-N frequency synthesizer when nonlinearities are present in the loop. These spurs are generated by the interaction between the nonlinearity and the quantization error that the digital Σ modulator (DDSM) introduces into the system. This paper analyzes the spurious effect of polynomial nonlinearities on fractional-N CP-PLLs equipped with multi-stage noise shaping (MASH) DDSMs of different orders. This leads to a proof of immunity from spurs for PLLs based on higher order MASH modulators in the case of certain polynomial nonlinearities.

A 0.20–2.43 GHz fractional-N frequency synthesizer with optimized VCO and reduced current mismatch CP

A 0.20–2.43 GHz fractional-N frequency synthesizer with optimized VCO and reduced current mismatch CP

A Ku-Band Fractional-N Frequency Synthesizer with Adaptive Loop Bandwidth Control

This paper presents a Ku-band fractional-N frequency synthesizer with adaptive loop bandwidth control (ALBC) to speed up the lock settling process and meanwhile ensure better phase noise and spur performance. The theoretical analysis and circuits implementation are discussed in detail. Other key modules of the frequency synthesizer such as broadband voltage-controlled oscillator (VCO) with auto frequency calibration (AFC) and programable frequency divider/charge pump/loop filter are designed for integrity and flexible configuration. The proposed frequency synthesizer is fabricated in 0.13 μm CMOS technology occupying 1.14 × 1.18 mm2 area including ESD/IOs and pads, and the area of the ALBC is only 55 × 76 μm2. The out frequency can cover from 11.37 GHz to 14.8 GHz with a frequency tuning range (FTR) of 26.2%. The phase noise is −112.5 dBc/Hz @ 1 MHz and −122.4 dBc/Hz @ 3 MHz at 13 GHz carrier frequency. Thanks to the proposed ALBC, the lock-time can be shortened by about 30% from about 36 μs to 24 μs. The chip area and power consumption of the proposed ALBC technology are slight, but the beneficial effect is significant.

MASH-Based Divider Controllers for Mitigation of Wandering Spurs in a Fractional-N Frequency Synthesizer

The divider controller can contribute significantly to the phase noise and spur pattern in the output of a nonlinear fractional-N frequency synthesizer. A type of time-varying spurs caused by a MASH DDSM divider controller, termed wandering spurs, has been observed in simulations and measurements of real synthesizers. In this work, we propose and analyze several MASH-based divider controller architectures that mitigate wandering spurs in a fractional-N frequency synthesizer.

A Fast Settling Multi-Standard CMOS Fractional-N Frequency Synthesizer for DECT/GSM/ CDMA &/NADC Wireless Communication Standards

A fast settling multi-standard CMOS fractional-N frequency synthesizer for DECT, GSM, CDMA and NADC wireless communication standards is proposed. This frequency synthesizer was simulated with ADS2008 in TSMC RF CMOS 0.18 µm. Frequency range is 824-1900 MHz, a switched capacitor LC-VCO was used in order to produce this frequency range. Frequency synthesizers have three main specifications of phase noise, settling time and power consumption. A new channel select circuit was designed instead of ∑∆ modulator to locate spur tones far from center frequency. A high reference frequency was used in order to reduce the VCO phase noise and locate the spur tones far from center frequency; these tones are produced by charge pump (reference spur) and N/N+1 divider (fractional spur). Two ways were used for phase noise optimization; in the first way phase noise was reduced by a low pass filter and a bypass capacitor (CT) that eliminate thermal noise and 2ω0 harmonics of tail current source; in the second way with biasing of VCO transistors only in saturation region preventing reduction of quality factor(Q) in tank circuit. These two ways in VCO of DECT were used, consequently the phase noise at 1875MHz center frequency was improved from -119.4 dBc/Hz at 3.4 MHz offset frequency to -144.3 dBc/Hz at 3.4 MHz offset frequency. The settling time for all standards was achieved less than almost 1 μs over the entire frequency range. For DECT synthesizer phase noise of -116.37 dBc/Hz at 3 MHz offset frequency was obtained, the first spur tone was located in 7.35 MHz offset from center frequency, also settling time of 350ns was obtained. The whole frequency synthesizer in loop1 (for DECT) draws 13 mA and in loop2 (for GSM900, CDMA &amp; NADC) draws 13.67 mA from a 1.8 V voltage supply.

A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking

This article presents a fractional-N frequency synthesizer architecture that is able to overcome the limitations of conventional bang-bang phase-locked loops. A digital frequencyerror recovery technique is introduced to enable fast lock, at no significant power or circuit overhead. A digital-to-time converter design with reduced static and dynamic nonlinearity is proposed, which allows for low-jitter and low-spur fractional-N operation. The phase-locked loop (PLL), implemented in a standard 28-nm CMOS process, occupies a core area of 0.17 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It covers a 1-GHz hop to within 70 ppm of the steady-state frequency value in 18.55 μs. The prototype achieves an rms-jitter (integrated from 1 kHz to 100 MHz) of 66.20 and 58.96 fs, in the fractional-N and integer-N modes, respectively. The worst-case in-band fractional spur is at -61 dBc. The total power consumption is 19.8 mW, which leads to a jitter-power figure-of-merit of -250.6 dB for the fractional-N channels.

A 22.5–31.2-GHz Continuously Tuning Frequency Synthesizer With 8.7-GHz Chirp for FMCW Applications

This letter presents a fractional-N frequency synthesizer with an ultrawideband continuously tuning range of 32.4% centered at 26.85- and 8.7-GHz chirp for frequency-modulated continuous-wave (FMCW) radars. The synthesizer uses a fractional-N 9-GHz charge-pump phase-locked loop (CPPLL) cascaded by an injection-locked frequency tripler (ILFT). A voltage-controlled oscillator (VCO) with transformer (TFM) coupling for an enhanced linear control voltage range, a better quality factor and good isolation from the load seen by the resonator, and a wide output voltage range charge-pump (CP) are used to achieve the ultrawideband CPPLL. The ILFT is implemented using a weakly coupled TFM for broadband locking range and 3-dB output power. The synthesizer is fabricated in the 40-nm CMOS technology and consumes 28.5 mW. The phase noise (PN) of the synthesizer at 27 GHz is -97.87 dBc/Hz at 1 MHz and the prototype is capable of generating a triangle or sawtooth chirp of 8.7-GHz modulation bandwidth with an rms FM error of 0.04% of BWchirp.